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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:09 -0700 Message-Id: <20170906160612.22769-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 29/32] target/arm: [a64] Move page and ss checks to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Henderson Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 25c6622825..9017e30510 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11206,6 +11206,7 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; ARMCPU *arm_cpu = arm_env_get_cpu(env); + int bound; dc->pc = dc->base.pc_first; dc->condjmp = 0; @@ -11254,8 +11255,14 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->is_ldex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); - dc->next_page_start = - (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + /* Bound the number of insns to execute to those left on the page. */ + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + + /* If architectural single step active, limit to 1. */ + if (dc->ss_active) { + bound = 1; + } + max_insns = MIN(max_insns, bound); init_tmp_a64_array(dc); @@ -11323,12 +11330,6 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) disas_a64_insn(env, dc); } - if (dc->base.is_jmp == DISAS_NEXT) { - if (dc->ss_active || dc->pc >= dc->next_page_start) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - } - dc->base.pc_next = dc->pc; translator_loop_temp_check(&dc->base); }