From patchwork Tue Sep 12 16:25:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9949595 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A135C6038F for ; Tue, 12 Sep 2017 16:27:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A52CF29037 for ; Tue, 12 Sep 2017 16:27:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 99A722903C; Tue, 12 Sep 2017 16:27:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D48F129037 for ; Tue, 12 Sep 2017 16:27:56 +0000 (UTC) Received: from localhost ([::1]:36889 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro2U-0002jo-0h for patchwork-qemu-devel@patchwork.kernel.org; Tue, 12 Sep 2017 12:27:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37841) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro03-0001eZ-GY for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro01-0006zX-V2 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:23 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34139) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro01-0006z1-OI for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:21 -0400 Received: by mail-pf0-x22a.google.com with SMTP id e1so19440286pfk.1 for ; Tue, 12 Sep 2017 09:25:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hFwvwZ150xcNrgqhl2aSty24LcbInIciYUKB6n8yIaE=; b=QmYHnxw2vKSdBablukeCFek7SOiDjmctIFo/k232MgR2NhNdd1QAtAL+5Fv1Tig3NX ySUFTfffq+yl6kkibDZmF9r1z/j/c9v5FJ47amNQo3R45d4dRK5kmyh1Uhcjla9iKZ9v +1rCwC5hJXaNTdaNYP/xx97yVh9ZuhQ2em0fw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hFwvwZ150xcNrgqhl2aSty24LcbInIciYUKB6n8yIaE=; b=g1WvVTp5pa86E9BgkRVX1EO3XLLLOC6P1TkPei1ifBvYz4OTzkxNljsoV6KhrBTYit 4rW3ilOP6+dxEi+OQPnxL7viKExpsCCt0CcDBp6a8+cNxB/bl7F17wqGbuZ24bTQdG3z jVRs36Nr2y4aWIM+D/U+90B0Vj9yRryyCJslR/AiqLUfMhL2DCpG6bD3dbB4FC1/iv8R biorrKi/abEWkEWQ56pKzY6YAkes7iGMCYlQyTYG6T+iwLESIQC3+E+nl0JMfwGC2kOh rWCph4zXu4e0j9FqEFJwIr+4sZqCwIM9yZN/2Kgem++PePEEnZxw+sHW0xrdO1qSRoG6 D4gw== X-Gm-Message-State: AHPjjUjYUYLvb3xoaquPSFrux4x8hllDYJVWuB6MDyrJJw+RImbXeItZ wKB2D0bkLvSGmIi5VZ6e5Q== X-Google-Smtp-Source: ADKCNb7nTwmhxbdTdyiGRjDEYCkLKggWtUxIRelnNhYGLqu0Qxnf8sTbM3diQRxCwSvBhcFZ6Whl3Q== X-Received: by 10.99.55.92 with SMTP id g28mr15461544pgn.59.1505233520511; Tue, 12 Sep 2017 09:25:20 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:00 -0700 Message-Id: <20170912162513.21694-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH v2 03/16] tcg: Add operations for host vectors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Nothing uses or implements them yet. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/tcg-opc.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg.h | 24 ++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 956fb1e9f3..edfdbf8798 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -206,6 +206,95 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, #undef TLADDR_ARGS #undef DATA64_ARGS + +/* Host integer vector operations. */ +/* These opcodes are required whenever the base vector size is enabled. */ + +DEF(mov_v64, 1, 1, 0, TCG_OPF_NOT_PRESENT) +DEF(mov_v128, 1, 1, 0, TCG_OPF_NOT_PRESENT) +DEF(mov_v256, 1, 1, 0, TCG_OPF_NOT_PRESENT) + +DEF(movi_v64, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(movi_v128, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(movi_v256, 1, 0, 1, TCG_OPF_NOT_PRESENT) + +DEF(ld_v64, 1, 1, 1, IMPL(TCG_TARGET_HAS_v64)) +DEF(ld_v128, 1, 1, 1, IMPL(TCG_TARGET_HAS_v128)) +DEF(ld_v256, 1, 1, 1, IMPL(TCG_TARGET_HAS_v256)) + +DEF(st_v64, 0, 2, 1, IMPL(TCG_TARGET_HAS_v64)) +DEF(st_v128, 0, 2, 1, IMPL(TCG_TARGET_HAS_v128)) +DEF(st_v256, 0, 2, 1, IMPL(TCG_TARGET_HAS_v256)) + +DEF(and_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(and_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(and_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(or_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(or_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(or_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(xor_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(xor_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(xor_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(add8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(add16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(add32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) + +DEF(add8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) + +DEF(add8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(sub8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(sub16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(sub32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) + +DEF(sub8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) + +DEF(sub8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +/* These opcodes are optional. + All element counts must be supported if any are. */ + +DEF(not_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v64)) +DEF(not_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v128)) +DEF(not_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v256)) + +DEF(andc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v64)) +DEF(andc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v128)) +DEF(andc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v256)) + +DEF(orc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v64)) +DEF(orc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v128)) +DEF(orc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v256)) + +DEF(neg8_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) +DEF(neg16_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) +DEF(neg32_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) + +DEF(neg8_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg16_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg32_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg64_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) + +DEF(neg8_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg16_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg32_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg64_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) + #undef IMPL #undef IMPL64 #undef DEF diff --git a/tcg/tcg.h b/tcg/tcg.h index f56ddac31d..69b1fdf457 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -166,6 +166,30 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_rem_i64 0 #endif +#ifndef TCG_TARGET_HAS_v64 +#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_andc_v64 0 +#define TCG_TARGET_HAS_orc_v64 0 +#define TCG_TARGET_HAS_not_v64 0 +#define TCG_TARGET_HAS_neg_v64 0 +#endif + +#ifndef TCG_TARGET_HAS_v128 +#define TCG_TARGET_HAS_v128 0 +#define TCG_TARGET_HAS_andc_v128 0 +#define TCG_TARGET_HAS_orc_v128 0 +#define TCG_TARGET_HAS_not_v128 0 +#define TCG_TARGET_HAS_neg_v128 0 +#endif + +#ifndef TCG_TARGET_HAS_v256 +#define TCG_TARGET_HAS_v256 0 +#define TCG_TARGET_HAS_andc_v256 0 +#define TCG_TARGET_HAS_orc_v256 0 +#define TCG_TARGET_HAS_not_v256 0 +#define TCG_TARGET_HAS_neg_v256 0 +#endif + /* For 32-bit targets, some sort of unsigned widening multiply is required. */ #if TCG_TARGET_REG_BITS == 32 \ && !(defined(TCG_TARGET_HAS_mulu2_i32) \