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[61.45.56.248]) by smtp.gmail.com with ESMTPSA id z76sm3274480pfi.117.2017.10.13.07.57.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2017 07:57:25 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Fri, 13 Oct 2017 23:57:11 +0900 Message-Id: <20171013145714.2740-3-shorne@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171013145714.2740-1-shorne@gmail.com> References: <20171013145714.2740-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL 2/5] target/openrisc: Make coreid and numcores variable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Previously coreid and numcores were hard coded as 0 and 1 respectively as OpenRISC QEMU did not have multicore support. Multicore support is now being added so these registers need to have configured values. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- target/openrisc/sys_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index abdef5d6a5..dc6e5cc7f2 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exception.h" +#include "sysemu/sysemu.h" #define TO_SPR(group, number) (((group) << 11) + (number)) @@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, return env->esr; case TO_SPR(0, 128): /* COREID */ - return 0; + return cpu->parent_obj.cpu_index; case TO_SPR(0, 129): /* NUMCORES */ - return 1; + return max_cpus; case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ idx = (spr - 1024);