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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id x1sm22719590pfh.113.2017.11.06.07.48.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Nov 2017 07:48:56 -0800 (PST) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 6 Nov 2017 07:48:08 -0800 Message-Id: <20171106154813.19936-26-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171106154813.19936-1-andrew.smirnov@gmail.com> References: <20171106154813.19936-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 25/30] i.MX: Add code to emulate i.MX7 SRC IP-block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrey Smirnov , Jason Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add minimal code needed to allow upstream Linux guest to boot. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daudé Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/misc/Makefile.objs | 1 + hw/misc/imx7_src.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++ include/hw/misc/imx7_src.h | 22 +++++++++++ 3 files changed, 116 insertions(+) create mode 100644 hw/misc/imx7_src.c create mode 100644 include/hw/misc/imx7_src.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index b578bd0cba..6c0bf4d519 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -41,6 +41,7 @@ obj-$(CONFIG_IMX) += imx7_iomuxc.o obj-$(CONFIG_IMX) += imx_flexcan.o obj-$(CONFIG_IMX) += imx7_adc.o obj-$(CONFIG_IMX) += imx7_gpr.o +obj-$(CONFIG_IMX) += imx7_src.o obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o obj-$(CONFIG_MAINSTONE) += mst_fpga.o diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c new file mode 100644 index 0000000000..2634e60ad7 --- /dev/null +++ b/hw/misc/imx7_src.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 SRC block emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/misc/imx7_src.h" +#include "qemu/log.h" + +static void imx7_src_reset(DeviceState *dev) +{ + IMX7SRCState *s = IMX7_SRC(dev); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static uint64_t imx7_src_read(void *opaque, hwaddr offset, + unsigned size) +{ + IMX7SRCState *s = opaque; + return s->regs[offset / sizeof(uint32_t)]; +} + +static void imx7_src_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + IMX7SRCState *s = opaque; + s->regs[offset / sizeof(uint32_t)] = value; +} + +static const struct MemoryRegionOps imx7_src_ops = { + .read = imx7_src_read, + .write = imx7_src_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +static void imx7_src_init(Object *obj) +{ + SysBusDevice *sd = SYS_BUS_DEVICE(obj); + IMX7SRCState *s = IMX7_SRC(obj); + + memory_region_init_io(&s->iomem, + obj, + &imx7_src_ops, + s, + TYPE_IMX7_SRC ".iomem", + sizeof(s->regs)); + sysbus_init_mmio(sd, &s->iomem); +} + +static const VMStateDescription vmstate_imx7_src = { + .name = TYPE_IMX7_SRC, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_NUM), + VMSTATE_END_OF_LIST() + }, +}; + +static void imx7_src_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = imx7_src_reset; + dc->vmsd = &vmstate_imx7_src; + dc->desc = "i.MX7 System Reset Controller"; +} + +static const TypeInfo imx7_src_info = { + .name = TYPE_IMX7_SRC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(IMX7SRCState), + .instance_init = imx7_src_init, + .class_init = imx7_src_class_init, +}; + +static void imx7_src_register_type(void) +{ + type_register_static(&imx7_src_info); +} +type_init(imx7_src_register_type) diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h new file mode 100644 index 0000000000..aaca091fa8 --- /dev/null +++ b/include/hw/misc/imx7_src.h @@ -0,0 +1,22 @@ +#ifndef IMX7_SRC_H +#define IMX7_SRC_H + +#include "hw/sysbus.h" + +enum IMX7SRCRegisters { + SRC_NUM = 0x1000 / sizeof(uint32_t) + 1, +}; + +typedef struct IMX7SRCState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + uint32_t regs[SRC_NUM]; +} IMX7SRCState; + +#define TYPE_IMX7_SRC "imx7-src" +#define IMX7_SRC(obj) OBJECT_CHECK(IMX7SRCState, (obj), TYPE_IMX7_SRC) + +#endif /* IMX7_SRC_H */