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X-Received-From: 2607:f8b0:400e:c05::243 X-Mailman-Approved-At: Tue, 19 Dec 2017 10:38:10 -0500 Subject: [Qemu-devel] [PATCH] linux-user: set P5600 as default for MIPS o32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: YunQiang Su Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP P5600 supports MIPS32r5, and is supported by qemu. The current 24Kf supports mips32r2 only, to execute r3/r5 binaries we need P5600. .CP1_fcr31_rw_bitmask for P5600 is also modified: to make FCR31_NAN2008 and FCR31_ABS2008 editable, otherwise only NAN2008 binaries are supported. Signed-off-by: YunQiang Su --- linux-user/main.c | 2 +- target/mips/translate_init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index f2b02a99a2..7c0bffeff6 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4323,7 +4323,7 @@ int main(int argc, char **argv, char **envp) #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) cpu_model = "5KEf"; #else - cpu_model = "24Kf"; + cpu_model = "P5600"; #endif #elif defined TARGET_OPENRISC cpu_model = "or1200"; diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c index c7ba6ee5f9..e3020619d2 100644 --- a/target/mips/translate_init.c +++ b/target/mips/translate_init.c @@ -404,7 +404,7 @@ const mips_def_t mips_defs[] = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID), .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), - .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .CP1_fcr31_rw_bitmask = 0xFF8FFFFF, .SEGBITS = 32, .PABITS = 40, .insn_flags = CPU_MIPS32R5 | ASE_MSA,