From patchwork Mon Dec 25 01:06:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haozhong Zhang X-Patchwork-Id: 10132195 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4682A602DC for ; Mon, 25 Dec 2017 01:09:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2FB0E28BDE for ; Mon, 25 Dec 2017 01:09:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2395828BE0; Mon, 25 Dec 2017 01:09:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 86A7F28BDE for ; Mon, 25 Dec 2017 01:09:44 +0000 (UTC) Received: from localhost ([::1]:49934 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eTHGx-0007vp-R0 for patchwork-qemu-devel@patchwork.kernel.org; Sun, 24 Dec 2017 20:09:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eTHED-00064a-1o for qemu-devel@nongnu.org; Sun, 24 Dec 2017 20:06:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eTHE9-0007nR-SJ for qemu-devel@nongnu.org; Sun, 24 Dec 2017 20:06:53 -0500 Received: from mga03.intel.com ([134.134.136.65]:31731) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eTHE9-0007mF-Iq for qemu-devel@nongnu.org; Sun, 24 Dec 2017 20:06:49 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Dec 2017 17:06:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,452,1508828400"; d="scan'208";a="5252900" Received: from hz-desktop.sh.intel.com (HELO localhost) ([10.239.159.142]) by orsmga007.jf.intel.com with ESMTP; 24 Dec 2017 17:06:45 -0800 From: Haozhong Zhang To: qemu-devel@nongnu.org Date: Mon, 25 Dec 2017 09:06:10 +0800 Message-Id: <20171225010611.32621-2-haozhong.zhang@intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171225010611.32621-1-haozhong.zhang@intel.com> References: <20171225010611.32621-1-haozhong.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.65 Subject: [Qemu-devel] [PATCH 1/2] util/pmem: add function to make writes to pmem persistent X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haozhong Zhang , Xiao Guangrong , mst@redhat.com, Stefan Hajnoczi , Igor Mammedov , Dan Williams Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The new function pmem_persistent() flushes the previous cached writes on the specified memory buffer, which ensures the write persistence if the buffer is in persistent memory. Signed-off-by: Haozhong Zhang --- include/qemu/pmem.h | 25 ++++++++++ util/Makefile.objs | 1 + util/pmem.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 158 insertions(+) create mode 100644 include/qemu/pmem.h create mode 100644 util/pmem.c diff --git a/include/qemu/pmem.h b/include/qemu/pmem.h new file mode 100644 index 0000000000..6593ae1d5c --- /dev/null +++ b/include/qemu/pmem.h @@ -0,0 +1,25 @@ +/* + * Helper functions to operate on persistent memory. + * + * Copyright (c) 2017 Intel Corporation. + * + * Author: Haozhong Zhang + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_PMEM_H +#define QEMU_PMEM_H + +/** + * Flush previous cached writes to the specified memory buffer. If the + * buffer is in persistent memory, this function will ensure the write + * persistence. + * + * @p: the pointer to the memory buffer + * @len: the length in bytes of the memory buffer + */ +void pmem_persistent(void *p, unsigned long len); + +#endif /* QEMU_PMEM_H */ diff --git a/util/Makefile.objs b/util/Makefile.objs index 2973b0a323..2614a84a9e 100644 --- a/util/Makefile.objs +++ b/util/Makefile.objs @@ -41,6 +41,7 @@ util-obj-y += timed-average.o util-obj-y += base64.o util-obj-y += log.o util-obj-y += pagesize.o +util-obj-y += pmem.o util-obj-y += qdist.o util-obj-y += qht.o util-obj-y += range.o diff --git a/util/pmem.c b/util/pmem.c new file mode 100644 index 0000000000..44be1dde58 --- /dev/null +++ b/util/pmem.c @@ -0,0 +1,132 @@ +/* + * Helper functions to operate on persistent memory. + * + * Copyright (c) 2017 Intel Corporation. + * + * Author: Haozhong Zhang + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/pmem.h" + +static size_t cache_line_size; + +typedef void (*cache_flush_func_t)(void *p); +typedef void (*store_fence_func_t)(void); + +static cache_flush_func_t cache_flush_func; +static store_fence_func_t store_fence_func; + +#if defined(__x86_64__) || defined(__i386__) + +#define CPUID_1_0_EBX_CLSIZE_MASK 0x0000ff00 +#define CPUID_1_0_EBX_CLSIZE_SHIFT 8 +#define CPUID_1_0_EDX_CLFLUSH (1U << 19) +#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) +#define CPUID_7_0_EBX_CLWB (1U << 24) + +static inline void cpuid(uint32_t function, uint32_t count, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) +{ + uint32_t vec[4]; + +#ifdef __x86_64__ + asm volatile("cpuid" + : "=a"(vec[0]), "=b"(vec[1]), + "=c"(vec[2]), "=d"(vec[3]) + : "0"(function), "c"(count) : "cc"); +#else + asm volatile("pusha\n\t" + "cpuid\n\t" + "mov %%eax, 0(%2)\n\t" + "mov %%ebx, 4(%2)\n\t" + "mov %%ecx, 8(%2)\n\t" + "mov %%edx, 12(%2)\n\t" + "popa" + : : "a"(function), "c"(count), "S"(vec) + : "memory", "cc"); +#endif + + if (eax) { + *eax = vec[0]; + } + if (ebx) { + *ebx = vec[1]; + } + if (ecx) { + *ecx = vec[2]; + } + if (edx) { + *edx = vec[3]; + } +} + +static void clflush(void *p) +{ + asm volatile("clflush %0" : "+m" (*(volatile char *)p)); +} + +static void clflushopt(void *p) +{ + asm volatile(".byte 0x66; clflush %0" : "+m" (*(volatile char *)p)); +} + +static void clwb(void *p) +{ + asm volatile(".byte 0x66; xsaveopt %0" : "+m" (*(volatile char *)p)); +} + +static void sfence(void) +{ + asm volatile("sfence" : : : "memory"); +} + +static void __attribute__((constructor)) init_funcs(void) +{ + uint32_t ebx, edx; + + cpuid(0x1, 0x0, NULL, &ebx, NULL, &edx); + + cache_line_size = ((ebx & CPUID_1_0_EBX_CLSIZE_MASK) >> + CPUID_1_0_EBX_CLSIZE_SHIFT) * 8; + assert(cache_line_size && !(cache_line_size & (cache_line_size - 1))); + + cpuid(0x7, 0x0, NULL, &ebx, NULL, NULL); + if (ebx & CPUID_7_0_EBX_CLWB) { + cache_flush_func = clwb; + } else if (ebx & CPUID_7_0_EBX_CLFLUSHOPT) { + cache_flush_func = clflushopt; + } else { + if (edx & CPUID_1_0_EDX_CLFLUSH) { + cache_flush_func = clflush; + } + } + + store_fence_func = sfence; +} + +#endif /* __x86_64__ || __i386__ */ + +void pmem_persistent(void *p, unsigned long len) +{ + uintptr_t s, e; + + if (!cache_flush_func || !store_fence_func) { + return; + } + + s = (uintptr_t)p & ~(cache_line_size - 1); + e = (uintptr_t)p + len; + + while (s < e) { + cache_flush_func((void *)s); + s += cache_line_size; + } + + store_fence_func(); +}