From patchwork Fri Jan 19 18:22:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 10175849 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4978960386 for ; Fri, 19 Jan 2018 18:25:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3361D269DA for ; Fri, 19 Jan 2018 18:25:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 24BE726E76; Fri, 19 Jan 2018 18:25:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 98DDE269DA for ; Fri, 19 Jan 2018 18:25:36 +0000 (UTC) Received: from localhost ([::1]:36508 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecbM7-0001Zd-Mw for patchwork-qemu-devel@patchwork.kernel.org; Fri, 19 Jan 2018 13:25:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35450) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecbJp-0007d4-57 for qemu-devel@nongnu.org; Fri, 19 Jan 2018 13:23:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecbJn-0008HL-Qs for qemu-devel@nongnu.org; Fri, 19 Jan 2018 13:23:12 -0500 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:43055) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ecbJn-0008GG-KM for qemu-devel@nongnu.org; Fri, 19 Jan 2018 13:23:11 -0500 Received: by mail-wr0-x241.google.com with SMTP id t16so2357044wrc.10 for ; Fri, 19 Jan 2018 10:23:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XK9va+Jr7wnzir1lQ+SLkliENWcyVi/bz/D/+OpNXQI=; b=S3PHU2gmTALWoobE6SxAuvF8ZR+mKdbHcLzb+AAXiIOUXofTRmcSMRkq81ObPZ7pov lyPyCvbxoS5mc914uuMTvYqjROLZFcgXxqrcf/jGMjRMIjnlOn3t3FxjAHgNK2xlM9c2 lSMffpsY8qiWVRPZFB7oapOkandAHApm4HT9M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XK9va+Jr7wnzir1lQ+SLkliENWcyVi/bz/D/+OpNXQI=; b=DM3ev92JZcYqjyebQ5BgNOo5e/X/2mQsK+aFUDNgTxfTeOt5VE9piTeEX8C2Q0L3sT 1N2pAUsHujQrMU+LVOdYK7Y+DfFIjzesfGgXxO1H7h37EnC3q1tUJKVFdTR6WbZHIY/K UFd2XwdJX4qnRMESEaQ099AhbT03qMApFZ7wTGzhNeo1T5qNYYOXuYDRvOhNd15N4bs8 t5XID22UDtHclW8mBsbEFvSKyofIzdUFigJjNbbc3v1pkknodGvled6k6c+5nVAefVWk 00Rfp2lDowm+cBsPepJ3awZhrjGB2S7QNJmRaoHtIL0hjZR6LeBggZlmApM7UN5cgbFI wv4g== X-Gm-Message-State: AKwxytfdCWc+n6qDs9XzXyg/u4ac9Y/T3PdWYXEkZ6ef1qSr1gIkatkr 4XKNgOOflRVI68eRosyi9FBQ3Z+FFmc= X-Google-Smtp-Source: ACJfBovWZ1S++IyDNtbk7Sk4SUBL+vDfuPJ9he1qjAcT9XDvkIycZBF+ZmjrhWUEzzmBenHxVyKRPg== X-Received: by 10.223.182.18 with SMTP id f18mr9596903wre.11.1516386190388; Fri, 19 Jan 2018 10:23:10 -0800 (PST) Received: from localhost.localdomain ([160.170.62.40]) by smtp.gmail.com with ESMTPSA id f48sm6263629wra.72.2018.01.19.10.23.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 10:23:09 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Fri, 19 Jan 2018 18:22:48 +0000 Message-Id: <20180119182248.10821-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119182248.10821-1-ard.biesheuvel@linaro.org> References: <20180119182248.10821-1-ard.biesheuvel@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v4 4/4] target/arm: enable user-mode SHA-3, SM3 and SHA-512 instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel , rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add support for the new ARMv8.2 SHA-3, SM3 and SHA-512 instructions to AArch64 user mode emulation. Signed-off-by: Ard Biesheuvel Reviewed-by: Peter Maydell --- linux-user/elfload.c | 18 ++++++++++++++++++ target/arm/cpu64.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 20f3d8c2c373..5d5aa26d2710 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,21 @@ enum { ARM_HWCAP_A64_SHA1 = 1 << 5, ARM_HWCAP_A64_SHA2 = 1 << 6, ARM_HWCAP_A64_CRC32 = 1 << 7, + ARM_HWCAP_A64_ATOMICS = 1 << 8, + ARM_HWCAP_A64_FPHP = 1 << 9, + ARM_HWCAP_A64_ASIMDHP = 1 << 10, + ARM_HWCAP_A64_CPUID = 1 << 11, + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, + ARM_HWCAP_A64_JSCVT = 1 << 13, + ARM_HWCAP_A64_FCMA = 1 << 14, + ARM_HWCAP_A64_LRCPC = 1 << 15, + ARM_HWCAP_A64_DCPOP = 1 << 16, + ARM_HWCAP_A64_SHA3 = 1 << 17, + ARM_HWCAP_A64_SM3 = 1 << 18, + ARM_HWCAP_A64_SM4 = 1 << 19, + ARM_HWCAP_A64_ASIMDDP = 1 << 20, + ARM_HWCAP_A64_SHA512 = 1 << 21, + ARM_HWCAP_A64_SVE = 1 << 22, }; #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +547,9 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); #undef GET_FEATURE return hwcaps; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6ed4..56d50ba57194 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -224,6 +224,9 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */