From patchwork Tue Feb 6 11:19:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 10202785 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AF36B60327 for ; Tue, 6 Feb 2018 11:22:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8107F28843 for ; Tue, 6 Feb 2018 11:22:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75D9928A9C; Tue, 6 Feb 2018 11:22:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4E3FA28A30 for ; Tue, 6 Feb 2018 11:22:16 +0000 (UTC) Received: from localhost ([::1]:57512 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej1KJ-00076s-Iw for patchwork-qemu-devel@patchwork.kernel.org; Tue, 06 Feb 2018 06:22:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59936) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej1Hq-0004vw-OC for qemu-devel@nongnu.org; Tue, 06 Feb 2018 06:19:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ej1Hl-00026q-Id for qemu-devel@nongnu.org; Tue, 06 Feb 2018 06:19:42 -0500 Received: from mail.ispras.ru ([83.149.199.45]:49312) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ej1Hl-00023h-5V for qemu-devel@nongnu.org; Tue, 06 Feb 2018 06:19:37 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id A24D4540093; Tue, 6 Feb 2018 14:19:35 +0300 (MSK) From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Date: Tue, 06 Feb 2018 14:19:37 +0300 Message-ID: <20180206111936.12592.68781.stgit@pasha-VirtualBox> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.45 Subject: [Qemu-devel] [PATCH v2] m68k: implement movep instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huth@tuxfamily.org, dovgaluk@ispras.ru, laurent@vivier.eu, pavel.dovgaluk@ispras.ru Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch implements movep instruction. It moves data between a data register and alternate bytes within the address space starting at the location specified and incrementing by two. It was designed for the original 68000 and used in firmwares for interfacing the 8-bit peripherals through the 16-bit data bus. Without this patch opcode for this instruction is recognized as some bitop. Signed-off-by: Pavel Dovgalyuk Signed-off-by: Mihail Abakumov --- v2: - disabled movep for Coldfire - fixed gen_store/load usage --- target/m68k/cpu.c | 3 +++ target/m68k/cpu.h | 1 + target/m68k/translate.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 98919b3..2b38b9b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -113,6 +113,7 @@ static void m68000_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_M68000); m68k_set_feature(env, M68K_FEATURE_USP); m68k_set_feature(env, M68K_FEATURE_WORD_INDEX); + m68k_set_feature(env, M68K_FEATURE_MOVEP); } static void m68020_cpu_initfn(Object *obj) @@ -135,6 +136,7 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_BKPT); m68k_set_feature(env, M68K_FEATURE_RTD); m68k_set_feature(env, M68K_FEATURE_CHK2); + m68k_set_feature(env, M68K_FEATURE_MOVEP); } #define m68030_cpu_initfn m68020_cpu_initfn @@ -145,6 +147,7 @@ static void m68040_cpu_initfn(Object *obj) m68020_cpu_initfn(obj); m68k_set_feature(env, M68K_FEATURE_M68040); + m68k_set_feature(env, M68K_FEATURE_MOVEP); } static void m68060_cpu_initfn(Object *obj) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 627fb78..1d79885 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -492,6 +492,7 @@ enum m68k_features { M68K_FEATURE_RTD, M68K_FEATURE_CHK2, M68K_FEATURE_M68040, /* instructions specific to MC68040 */ + M68K_FEATURE_MOVEP, }; static inline int m68k_feature(CPUM68KState *env, int feature) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 34db97b..ddb5b34 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2078,6 +2078,55 @@ DISAS_INSN(movem) tcg_temp_free(addr); } +DISAS_INSN(movep) +{ + uint8_t i; + uint8_t op; + uint16_t displ; + TCGv reg; + TCGv addr; + TCGv abuf; + TCGv dbuf; + + op = (insn >> 6) & 7; + displ = read_im16(env, s); + + addr = AREG(insn, 0); + reg = DREG(insn, 9); + + abuf = tcg_temp_new(); + tcg_gen_addi_i32(abuf, addr, displ); + dbuf = tcg_temp_new(); + + if (op & 1) { + i = 4; + } else { + i = 2; + } + + if (op & 2) { + for ( ; i > 0 ; i--) { + tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8); + gen_store(s, OS_BYTE, abuf, dbuf, IS_USER(s)); + if (i > 1) { + tcg_gen_addi_i32(abuf, abuf, 2); + } + } + } else { + tcg_gen_movi_i32(reg, 0); + for ( ; i > 0 ; i--) { + dbuf = gen_load(s, OS_BYTE, abuf, 1, IS_USER(s)); + tcg_gen_or_i32(reg, reg, dbuf); + if (i > 1) { + tcg_gen_shli_i32(reg, reg, 8); + tcg_gen_addi_i32(abuf, abuf, 2); + } + } + } + tcg_temp_free(abuf); + tcg_temp_free(dbuf); +} + DISAS_INSN(bitop_im) { int opsize; @@ -5675,9 +5724,13 @@ void register_m68k_insns (CPUM68KState *env) INSN(chk2, 00c0, f9c0, CHK2); INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); BASE(bitop_reg, 0100, f1c0); + INSN(movep, 0108, f1f8, MOVEP); BASE(bitop_reg, 0140, f1c0); + INSN(movep, 0148, f1f8, MOVEP); BASE(bitop_reg, 0180, f1c0); + INSN(movep, 0188, f1f8, MOVEP); BASE(bitop_reg, 01c0, f1c0); + INSN(movep, 01c8, f1f8, MOVEP); INSN(arith_im, 0280, fff8, CF_ISA_A); INSN(arith_im, 0200, ff00, M68000); INSN(undef, 02c0, ffc0, M68000);