From patchwork Wed Feb 7 11:17:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 10204995 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D3C97602D8 for ; Wed, 7 Feb 2018 11:22:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C690528AC0 for ; Wed, 7 Feb 2018 11:22:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B906F28AEF; Wed, 7 Feb 2018 11:22:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5789D28634 for ; Wed, 7 Feb 2018 11:22:29 +0000 (UTC) Received: from localhost ([::1]:51913 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejNo4-0001Fz-H7 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 07 Feb 2018 06:22:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejNjZ-0005Fl-H2 for qemu-devel@nongnu.org; Wed, 07 Feb 2018 06:17:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejNjY-0005js-J1 for qemu-devel@nongnu.org; Wed, 07 Feb 2018 06:17:49 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:54084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ejNjY-0005jA-Bq for qemu-devel@nongnu.org; Wed, 07 Feb 2018 06:17:48 -0500 Received: by mail-wm0-x244.google.com with SMTP id t74so2448365wme.3 for ; Wed, 07 Feb 2018 03:17:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0E8xRuXjt6tHNmF2FMIetywkxa2Ci1p121AN/nSrBIE=; b=Gx4630wzk12pmYyYy2oYpPBcQ+AVqZYzK5pyWAxkFPBOzCyJ3eLK7zSle3irFxPj54 TONTMo1qCXo8iXk19ScQXko9y5/lnDik0De0pxea3LS09m5FrLem5PVZaJEB+Ynydfyb qJOK3EFljze/VzDLsMlee3yehlIvi9yWcYdig= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0E8xRuXjt6tHNmF2FMIetywkxa2Ci1p121AN/nSrBIE=; b=ihNLq7VhtY9wJ6UTYDTmS1m9jz0Ci2Ob54Cc84x2Y25XZn8GToFQSiIQOVB9Munm4v aHUjlRC1qKpsG7VFVn2gW9l2s4r5olvgYmk8iHabCl3j7GsXKtDXup0+sWTvhWsWRl/9 wZbHrxW8IlWMWawOE3kRSCcdwWLABGInAykNqqwGxW/P8pmVnC6HNJNWYjehgeC6TPnR l8rGpJNReeju5CQhzB/6PGgGxn5znOCA3VOU7JyFFkG3D0kYws7UuJ54+LlXvPbqraN5 Et5dtZuOpTnicVh6yxha3HKYi0m3+Hf0kZMtdBZz7GrdmgW79nOzOzDv+RIJ0ICCPkk5 lWaA== X-Gm-Message-State: APf1xPDOH/t3J+D7s4RaVRQzWK3hhQ8c0Voncul6yYV+58AoL3OxchR3 +Nm+XaCnt1tS32tswf/b4x8bpIuOIgQ= X-Google-Smtp-Source: AH8x224qkR/FMyZ+oe2JyGCpUo+/OgQmlVr0L4DLoFnOkwvkeQYkGkVUbh/CNEwtrC+PjDIhUsYn5w== X-Received: by 10.28.47.80 with SMTP id v77mr4263229wmv.23.1518002267143; Wed, 07 Feb 2018 03:17:47 -0800 (PST) Received: from localhost.localdomain ([196.85.252.149]) by smtp.gmail.com with ESMTPSA id h32sm627629wrf.65.2018.02.07.03.17.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Feb 2018 03:17:46 -0800 (PST) From: Ard Biesheuvel To: qemu-devel@nongnu.org Date: Wed, 7 Feb 2018 11:17:29 +0000 Message-Id: <20180207111729.15737-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180207111729.15737-1-ard.biesheuvel@linaro.org> References: <20180207111729.15737-1-ard.biesheuvel@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to AArch64 user mode emulation. Signed-off-by: Ard Biesheuvel --- linux-user/elfload.c | 19 +++++++++++++++++++ target/arm/cpu64.c | 4 ++++ 2 files changed, 23 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 20f3d8c2c373..7922ab8eab79 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -512,6 +512,21 @@ enum { ARM_HWCAP_A64_SHA1 = 1 << 5, ARM_HWCAP_A64_SHA2 = 1 << 6, ARM_HWCAP_A64_CRC32 = 1 << 7, + ARM_HWCAP_A64_ATOMICS = 1 << 8, + ARM_HWCAP_A64_FPHP = 1 << 9, + ARM_HWCAP_A64_ASIMDHP = 1 << 10, + ARM_HWCAP_A64_CPUID = 1 << 11, + ARM_HWCAP_A64_ASIMDRDM = 1 << 12, + ARM_HWCAP_A64_JSCVT = 1 << 13, + ARM_HWCAP_A64_FCMA = 1 << 14, + ARM_HWCAP_A64_LRCPC = 1 << 15, + ARM_HWCAP_A64_DCPOP = 1 << 16, + ARM_HWCAP_A64_SHA3 = 1 << 17, + ARM_HWCAP_A64_SM3 = 1 << 18, + ARM_HWCAP_A64_SM4 = 1 << 19, + ARM_HWCAP_A64_ASIMDDP = 1 << 20, + ARM_HWCAP_A64_SHA512 = 1 << 21, + ARM_HWCAP_A64_SVE = 1 << 22, }; #define ELF_HWCAP get_elf_hwcap() @@ -532,6 +547,10 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); + GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); + GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); + GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); + GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); #undef GET_FEATURE return hwcaps; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6ed4..1c330adc281b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -224,6 +224,10 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_AES); set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */