| Message ID | 20180323131715.29739-1-jcmvbkbc@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Max, On 03/23/2018 10:17 AM, Max Filippov wrote: > Change frequency of the core used in tests so that clock cycle takes > exactly 64ns. Change icount power used in tests to 6, so that each > instruction takes exactly 1 clock cycle. With these changes the > assumptions of the xtensa timers test are correct and the test must > always pass. > > Longer story: > http://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg04326.html Would be great to have it in this commit message. > > Cc: Pavel Dovgaluk <Pavel.Dovgaluk@ispras.ru> > Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> > --- > target/xtensa/core-dc232b.c | 2 +- > tests/tcg/xtensa/Makefile | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/xtensa/core-dc232b.c b/target/xtensa/core-dc232b.c > index aa07018af4e7..8846336f5cfa 100644 > --- a/target/xtensa/core-dc232b.c > +++ b/target/xtensa/core-dc232b.c > @@ -47,7 +47,7 @@ static XtensaConfig dc232b __attribute__((unused)) = { > } > }, > .isa_internal = &xtensa_modules, > - .clock_freq_khz = 10000, > + .clock_freq_khz = 15625, What about using self-explicit: .clock_freq_khz = (NANOSECONDS_PER_SECOND / 64) / 1000; > DEFAULT_SECTIONS > }; > > diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile > index 2882c431e4a9..091518c05583 100644 > --- a/tests/tcg/xtensa/Makefile > +++ b/tests/tcg/xtensa/Makefile > @@ -5,7 +5,7 @@ CROSS=xtensa-$(CORE)-elf- > > ifndef XT > SIM = ../../../xtensa-softmmu/qemu-system-xtensa > -SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting -icount 7 $(EXTFLAGS) -kernel > +SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel > SIMDEBUG = -s -S > else > SIM = xt-run > Regards, Phil.
diff --git a/target/xtensa/core-dc232b.c b/target/xtensa/core-dc232b.c index aa07018af4e7..8846336f5cfa 100644 --- a/target/xtensa/core-dc232b.c +++ b/target/xtensa/core-dc232b.c @@ -47,7 +47,7 @@ static XtensaConfig dc232b __attribute__((unused)) = { } }, .isa_internal = &xtensa_modules, - .clock_freq_khz = 10000, + .clock_freq_khz = 15625, DEFAULT_SECTIONS }; diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index 2882c431e4a9..091518c05583 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -5,7 +5,7 @@ CROSS=xtensa-$(CORE)-elf- ifndef XT SIM = ../../../xtensa-softmmu/qemu-system-xtensa -SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting -icount 7 $(EXTFLAGS) -kernel +SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting -icount 6 $(EXTFLAGS) -kernel SIMDEBUG = -s -S else SIM = xt-run
Change frequency of the core used in tests so that clock cycle takes exactly 64ns. Change icount power used in tests to 6, so that each instruction takes exactly 1 clock cycle. With these changes the assumptions of the xtensa timers test are correct and the test must always pass. Longer story: http://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg04326.html Cc: Pavel Dovgaluk <Pavel.Dovgaluk@ispras.ru> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> --- target/xtensa/core-dc232b.c | 2 +- tests/tcg/xtensa/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)