| Message ID | 20180326001421.0E0937456D7@zero.eik.bme.hu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Mar 26, 2018 at 01:54:28AM +0200, BALATON Zoltan wrote: > According to the Vector/SIMD extension documentation bit 6 that is > currently masked is valid (listed as transient bit) but bits 7 and 8 > should be reserved instead. Fix the mask to match this. What document can I find information on dstst in? The ISA documents I have handy are either too early (the instruction didn't exist yet) or too late (the instruction was considered obsolete and no details are given). > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> > --- > target/ppc/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 3457d29..b0d79a3 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -6561,7 +6561,7 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), > GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), > GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), > GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), > -GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), > +GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), > GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), > GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), > GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
On Mon, 26 Mar 2018, David Gibson wrote: > On Mon, Mar 26, 2018 at 01:54:28AM +0200, BALATON Zoltan wrote: >> According to the Vector/SIMD extension documentation bit 6 that is >> currently masked is valid (listed as transient bit) but bits 7 and 8 >> should be reserved instead. Fix the mask to match this. > > What document can I find information on dstst in? The ISA documents I > have handy are either too early (the instruction didn't exist yet) or > too late (the instruction was considered obsolete and no details are > given). I've found it in "PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual" Version 2.06 which was the first one Google found. According to this document dstst should have the same reserved bits as dst. Regards, BALATON Zoltan
On Mon, Mar 26, 2018 at 01:54:28AM +0200, BALATON Zoltan wrote: > According to the Vector/SIMD extension documentation bit 6 that is > currently masked is valid (listed as transient bit) but bits 7 and 8 > should be reserved instead. Fix the mask to match this. > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Applied to ppc-for-2.13, thanks. > --- > target/ppc/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 3457d29..b0d79a3 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -6561,7 +6561,7 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), > GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), > GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), > GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), > -GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), > +GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), > GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), > GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), > GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
On Mon, Mar 26, 2018 at 05:24:12AM +0200, BALATON Zoltan wrote: > On Mon, 26 Mar 2018, David Gibson wrote: > > On Mon, Mar 26, 2018 at 01:54:28AM +0200, BALATON Zoltan wrote: > > > According to the Vector/SIMD extension documentation bit 6 that is > > > currently masked is valid (listed as transient bit) but bits 7 and 8 > > > should be reserved instead. Fix the mask to match this. > > > > What document can I find information on dstst in? The ISA documents I > > have handy are either too early (the instruction didn't exist yet) or > > too late (the instruction was considered obsolete and no details are > > given). > > I've found it in "PowerPC Microprocessor Family: Vector/SIMD Multimedia > Extension Technology Programming Environments Manual" Version 2.06 which was > the first one Google found. According to this document dstst should have the > same reserved bits as dst. Thanks.
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3457d29..b0d79a3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6561,7 +6561,7 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), -GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), +GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
According to the Vector/SIMD extension documentation bit 6 that is currently masked is valid (listed as transient bit) but bits 7 and 8 should be reserved instead. Fix the mask to match this. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> --- target/ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)