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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id n2sm698482lji.75.2018.03.28.09.39.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Mar 2018 09:40:01 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Wed, 28 Mar 2018 09:39:43 -0700 Message-Id: <20180328163943.23783-1-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH] target/xtensa: fix flush_window_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP flush_window_regs uses wrong stack frame to save overflow registers in call8 and call12 frames, which results in wrong register values in callers of a function that received a signal. Reimplement flush_window_regs closely following window overflow sequence. Signed-off-by: Max Filippov --- linux-user/signal.c | 55 +++++++++++++++++++++++------------------------------ 1 file changed, 24 insertions(+), 31 deletions(-) diff --git a/linux-user/signal.c b/linux-user/signal.c index 2ea3e0321f4d..33d5ced30c98 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -7094,52 +7094,45 @@ static abi_ulong get_sigframe(struct target_sigaction *sa, static int flush_window_regs(CPUXtensaState *env) { - const uint32_t nareg_mask = env->config->nareg - 1; uint32_t wb = env->sregs[WINDOW_BASE]; - uint32_t ws = (xtensa_replicate_windowstart(env) >> (wb + 1)) & - ((1 << env->config->nareg / 4) - 1); - uint32_t d = ctz32(ws) + 1; - uint32_t sp; - abi_long ret = 0; - - wb += d; - ws >>= d; + uint32_t ws = xtensa_replicate_windowstart(env) >> (wb + 1); + unsigned d = ctz32(ws) + 1; + unsigned i; + int ret = 0; - xtensa_sync_phys_from_window(env); - sp = env->phys_regs[(wb * 4 + 1) & nareg_mask]; + for (i = d; i < env->config->nareg / 4; i += d) { + uint32_t ssp, osp; + unsigned j; - while (ws && ret == 0) { - int d; - int i; - int idx; + ws >>= d; + xtensa_rotate_window(env, d); if (ws & 0x1) { - ws >>= 1; + ssp = env->regs[5]; d = 1; } else if (ws & 0x2) { - ws >>= 2; + ssp = env->regs[9]; + ret |= get_user_ual(osp, env->regs[1] - 12); + osp -= 32; d = 2; - for (i = 0; i < 4; ++i) { - idx = (wb * 4 + 4 + i) & nareg_mask; - ret |= put_user_ual(env->phys_regs[idx], sp + (i - 12) * 4); - } } else if (ws & 0x4) { - ws >>= 3; + ssp = env->regs[13]; + ret |= get_user_ual(osp, env->regs[1] - 12); + osp -= 48; d = 3; - for (i = 0; i < 8; ++i) { - idx = (wb * 4 + 4 + i) & nareg_mask; - ret |= put_user_ual(env->phys_regs[idx], sp + (i - 16) * 4); - } } else { g_assert_not_reached(); } - sp = env->phys_regs[((wb + d) * 4 + 1) & nareg_mask]; - for (i = 0; i < 4; ++i) { - idx = (wb * 4 + i) & nareg_mask; - ret |= put_user_ual(env->phys_regs[idx], sp + (i - 4) * 4); + + for (j = 0; j < 4; ++j) { + ret |= put_user_ual(env->regs[j], ssp - 16 + j * 4); + } + for (j = 4; j < d * 4; ++j) { + ret |= put_user_ual(env->regs[j], osp - 16 + j * 4); } - wb += d; } + xtensa_rotate_window(env, d); + g_assert(env->sregs[WINDOW_BASE] == wb); return ret == 0; }