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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id o11-v6sm519343ljc.77.2018.05.16.11.52.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 11:52:06 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 20:51:20 +0200 Message-Id: <20180516185146.30708-13-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180516185146.30708-1-edgar.iglesias@gmail.com> References: <20180516185146.30708-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v3 12/38] target-microblaze: Remove pointer indirection for ld/st addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: "Edgar E. Iglesias" Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 3431a07b99..5ef978e897 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -848,7 +848,7 @@ static void dec_imm(DisasContext *dc) dc->clear_imm = 0; } -static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) +static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 t) { bool extimm = dc->tb_flags & IMM_FLAG; /* Should be set to true if r1 is used by loadstores. */ @@ -863,10 +863,10 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) if (!dc->type_b) { /* If any of the regs is r0, return the value of the other reg. */ if (dc->ra == 0) { - tcg_gen_mov_i32(*t, cpu_R[dc->rb]); + tcg_gen_mov_i32(t, cpu_R[dc->rb]); return; } else if (dc->rb == 0) { - tcg_gen_mov_i32(*t, cpu_R[dc->ra]); + tcg_gen_mov_i32(t, cpu_R[dc->ra]); return; } @@ -874,27 +874,27 @@ static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t) stackprot = true; } - tcg_gen_add_i32(*t, cpu_R[dc->ra], cpu_R[dc->rb]); + tcg_gen_add_i32(t, cpu_R[dc->ra], cpu_R[dc->rb]); if (stackprot) { - gen_helper_stackprot(cpu_env, *t); + gen_helper_stackprot(cpu_env, t); } return; } /* Immediate. */ if (!extimm) { if (dc->imm == 0) { - tcg_gen_mov_i32(*t, cpu_R[dc->ra]); + tcg_gen_mov_i32(t, cpu_R[dc->ra]); return; } - tcg_gen_movi_i32(*t, (int32_t)((int16_t)dc->imm)); - tcg_gen_add_i32(*t, cpu_R[dc->ra], *t); + tcg_gen_movi_i32(t, (int32_t)((int16_t)dc->imm)); + tcg_gen_add_i32(t, cpu_R[dc->ra], t); } else { - tcg_gen_add_i32(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); + tcg_gen_add_i32(t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); } if (stackprot) { - gen_helper_stackprot(cpu_env, *t); + gen_helper_stackprot(cpu_env, t); } return; } @@ -929,7 +929,7 @@ static void dec_load(DisasContext *dc) t_sync_flags(dc); addr = tcg_temp_new_i32(); - compute_ldst_addr(dc, &addr); + compute_ldst_addr(dc, addr); /* * When doing reverse accesses we need to do two things. @@ -1041,7 +1041,7 @@ static void dec_store(DisasContext *dc) sync_jmpstate(dc); /* SWX needs a temp_local. */ addr = ex ? tcg_temp_local_new_i32() : tcg_temp_new_i32(); - compute_ldst_addr(dc, &addr); + compute_ldst_addr(dc, addr); if (ex) { /* swx */ TCGv_i32 tval;