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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id p18-v6sm566716lfd.91.2018.05.16.11.52.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 May 2018 11:52:36 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Wed, 16 May 2018 20:51:39 +0200 Message-Id: <20180516185146.30708-32-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180516185146.30708-1-edgar.iglesias@gmail.com> References: <20180516185146.30708-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v3 31/38] target-microblaze: Simplify address computation using tcg_gen_addi_i32() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: "Edgar E. Iglesias" Simplify address computation using tcg_gen_addi_i32(). tcg_gen_addi_i32() already optimizes the case when the immediate is zero. No functional change. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé --- target/microblaze/translate.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 39c4d0654e..44395cf189 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -899,12 +899,7 @@ static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) /* Immediate. */ t32 = tcg_temp_new_i32(); if (!extimm) { - if (dc->imm == 0) { - tcg_gen_mov_i32(t32, cpu_R[dc->ra]); - } else { - tcg_gen_movi_i32(t32, (int32_t)((int16_t)dc->imm)); - tcg_gen_add_i32(t32, cpu_R[dc->ra], t32); - } + tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); } else { tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); }