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[v4,09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU

Message ID 20180523224745.30402-2-edgar.iglesias@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Edgar E. Iglesias May 23, 2018, 10:47 p.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Conditionalize setting of PVR11_USE_MMU on the use_mmu
CPU property, otherwise we may incorrectly advertise an
MMU via PVR when the core in fact has none.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/cpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Alistair Francis May 23, 2018, 10:56 p.m. UTC | #1 
On Wed, May 23, 2018 at 3:47 PM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Conditionalize setting of PVR11_USE_MMU on the use_mmu
> CPU property, otherwise we may incorrectly advertise an
> MMU via PVR when the core in fact has none.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/microblaze/cpu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 06476f6efc..a6f1ce6549 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -201,7 +201,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                                          PVR5_DCACHE_WRITEBACK_MASK : 0;
>
>      env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
> -    env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
> +    env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
> +                        16 << 17;
>
>      mcc->parent_realize(dev, errp);
>  }
> --
> 2.14.1
>
>
Richard Henderson May 25, 2018, 2:10 p.m. UTC | #2 
On 05/23/2018 03:47 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Conditionalize setting of PVR11_USE_MMU on the use_mmu
> CPU property, otherwise we may incorrectly advertise an
> MMU via PVR when the core in fact has none.
> 
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target/microblaze/cpu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox

Patch

diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 06476f6efc..a6f1ce6549 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -201,7 +201,8 @@  static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                                         PVR5_DCACHE_WRITEBACK_MASK : 0;
 
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
-    env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
+    env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
+                        16 << 17;
 
     mcc->parent_realize(dev, errp);
 }