@@ -360,8 +360,10 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
{
+ MicroBlazeCPU *cpu = mb_env_get_cpu(env);
+
/* Are we in nommu mode?. */
- if (!(env->sregs[SR_MSR] & MSR_VM)) {
+ if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
return MMU_NOMMU_IDX;
}
@@ -58,8 +58,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
int prot;
/* Translate if the MMU is available and enabled. */
- if (cpu->cfg.use_mmu && (env->sregs[SR_MSR] & MSR_VM)
- && mmu_idx != MMU_NOMMU_IDX) {
+ if (mmu_idx != MMU_NOMMU_IDX) {
uint32_t vaddr, paddr;
struct microblaze_mmu_lookup lu;
@@ -270,9 +269,10 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
CPUMBState *env = &cpu->env;
target_ulong vaddr, paddr = 0;
struct microblaze_mmu_lookup lu;
+ int mmu_idx = cpu_mmu_index(env, false);
unsigned int hit;
- if (env->sregs[SR_MSR] & MSR_VM) {
+ if (mmu_idx != MMU_NOMMU_IDX) {
hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
if (hit) {
vaddr = addr & TARGET_PAGE_MASK;