From patchwork Mon Jun 18 15:50:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Programmingkid X-Patchwork-Id: 10472159 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E2A096029B for ; Mon, 18 Jun 2018 15:52:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D290A28A0C for ; Mon, 18 Jun 2018 15:52:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C6A5F28A22; Mon, 18 Jun 2018 15:52:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 65EA628A0C for ; Mon, 18 Jun 2018 15:52:26 +0000 (UTC) Received: from localhost ([::1]:35446 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUwS9-0004Of-8f for patchwork-qemu-devel@patchwork.kernel.org; Mon, 18 Jun 2018 11:52:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fUwQT-0003nk-Ui for qemu-devel@nongnu.org; Mon, 18 Jun 2018 11:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fUwQQ-0008Fk-TE for qemu-devel@nongnu.org; Mon, 18 Jun 2018 11:50:42 -0400 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:54264) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fUwQQ-0008FP-Er; Mon, 18 Jun 2018 11:50:38 -0400 Received: by mail-it0-x243.google.com with SMTP id a195-v6so12720200itd.3; Mon, 18 Jun 2018 08:50:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=PgLSQ8ZSqHjnG5SDV0aKXI5pLrqyw5SWdxvHi2mdSc0=; b=ndmATZiBuB0nFXHpnVqLCSmq+yAZ6J6K/LiGzkVTOHZOseizhqm7VGVOCjrxFOlmrx ofcY/7tvrmW6N0lh0qkUoUUJozAX4IjRKni9S/TEBVyUVPwifq3LJqJ4McmcAYpCu67y +EwoETkfibonlfgoLgWKPpWJsPtURLxx1OgQXS5GsKUbNvugunb+7ooKfcxRO+utMMon oR6MGaa+uAyhrSuxE2fIXu1djiwSRyuswu/X7T41JKQcLEjdj6skn6UdVxvW4O7q0rRO hLlGJ545BzAZUx1k1x1FIV2rB1W0W/TUCurRoa2CU9z0IZbac2PhNrGC7N4T7tYm//bJ gH8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=PgLSQ8ZSqHjnG5SDV0aKXI5pLrqyw5SWdxvHi2mdSc0=; b=h5u+1qJ8D/+B2WFBoZabLKMJDKsauao4PgCMw/6m8BNLk0JKkRkVkNswumW+ci4sW9 eQUpjpy9HOXXQIjUPBmPMtX/gRy39V3EKIB1OgKG04i5ft9AuZwcy6n9s5ePvxI/as7z kPWI7d+5lJJoNzjOGZFhZ6LsCbfNjKn0b6Y4yGMn1xE+6hN6nIelvdVCfbIhvZ4IuBMB 14Ht5L69ktg/e5FQzENT8mXxWq9ePDpEe554k9uLSfmVpIiwEnMAS7S6IY5I7iCZXiM+ /oQ3o1iSnBSxDqG5H2TkCj+xmS23anxZyw+Pf8PXwPB95Sl8RDevdPb9sNa5Pr1bziVz B4dg== X-Gm-Message-State: APt69E2Ws59Q9vb9Cv2ghG8osrfRFZtIcJx72HKPGI9RUSW9THQ1Ka8H VJX7waYCxXqd+9tqGVDj0x0= X-Google-Smtp-Source: ADUXVKJTNp73doQzUAC4IY5N20UeAyCcjHB7P69wn5Xz8+wPx13DIqa37VqdNKzAzkC6BJaOmwQm6Q== X-Received: by 2002:a24:6f8f:: with SMTP id x137-v6mr9579294itb.121.1529337037617; Mon, 18 Jun 2018 08:50:37 -0700 (PDT) Received: from localhost.localdomain ([69.14.184.20]) by smtp.gmail.com with ESMTPSA id 81-v6sm6218507iou.73.2018.06.18.08.50.35 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 18 Jun 2018 08:50:36 -0700 (PDT) From: John Arbuckle To: peter.maydell@linaro.org, david@gibson.dropbear.id.au, qemu-devel@nongnu.org, aurelien@aurel32.net, qemu-ppc@nongnu.org, agraf@suse.de Date: Mon, 18 Jun 2018 11:50:24 -0400 Message-Id: <20180618155024.1942-1-programmingkidx@gmail.com> X-Mailer: git-send-email 2.14.3 (Apple Git-98) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4001:c0b::243 Subject: [Qemu-devel] [PATCH v2] fpu_helper.c: fix helper_fpscr_clrbit() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Arbuckle Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Fix the helper_fpscr_clrbit() function so it correctly sets the FEX and VX bits. Determining the value for the Floating Point Status and Control Register's (FPSCR) FEX bit is suppose to be done like this: FEX = (VX & VE) | (OX & OE) | (UX & UE) | (ZX & ZE) | (XX & XE)) It is described as "the logical OR of all the floating-point exception bits masked by their respective enable bits". It was not implemented correctly. The value of FEX would stay on even when all other bits were set to off. The VX bit is described as "the logical OR of all of the invalid operation exceptions". This bit was also not implemented correctly. It too would stay on when all the other bits were set to off. My main source of information is an IBM document called: PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors Page 62 is where the FPSCR information is located. This is an older copy than the one I use but it is still very useful: https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html I use a G3 and G5 iMac to compare bit values with QEMU. This patch fixed all the problems I was having with these bits. Signed-off-by: John Arbuckle --- v2 changes: - Removed the FPSCR_VX case because it is not a bit that can be set directly. - Replaced previous code with predefined macros fpscr_ix and fpscr_eex. target/ppc/fpu_helper.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index d31a933cbb..7714bfe0f9 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -325,6 +325,34 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) case FPSCR_RN: fpscr_set_rounding_mode(env); break; + case FPSCR_VXSNAN: + case FPSCR_VXISI: + case FPSCR_VXIDI: + case FPSCR_VXZDZ: + case FPSCR_VXIMZ: + case FPSCR_VXVC: + case FPSCR_VXSOFT: + case FPSCR_VXSQRT: + case FPSCR_VXCVI: + if (!fpscr_ix) { + /* Set VX bit to zero */ + env->fpscr &= ~(1 << FPSCR_VX); + } + break; + case FPSCR_OX: + case FPSCR_UX: + case FPSCR_ZX: + case FPSCR_XX: + case FPSCR_VE: + case FPSCR_OE: + case FPSCR_UE: + case FPSCR_ZE: + case FPSCR_XE: + if (!fpscr_eex) { + /* Set the FEX bit */ + env->fpscr &= ~(1 << FPSCR_FEX); + } + break; default: break; }