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(jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id l14-v6sm460143ljh.91.2018.08.28.18.17.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Aug 2018 18:17:10 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 28 Aug 2018 18:16:52 -0700 Message-Id: <20180829011652.4466-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180829011652.4466-1-jcmvbkbc@gmail.com> References: <20180829011652.4466-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::244 Subject: [Qemu-devel] [PATCH v2 2/2] tests/tcg/xtensa: add test for failed memory transactions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Max Filippov Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Failed memory transactions should raise exceptions 14 (for fetch) or 15 (for load/store) with XEA2. Memory accesses that result in TLB miss followed by an attempt to load PTE from physical memory which fails should raise InstTLBMiss or LoadStoreTLBMiss with XEA2. Signed-off-by: Max Filippov --- Changes v1->v2: - add tests that attempt TLB autorefill from the physically unmapped addresses. tests/tcg/xtensa/Makefile | 1 + tests/tcg/xtensa/test_phys_mem.S | 124 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 tests/tcg/xtensa/test_phys_mem.S diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index 091518c05583..2f5691f75b09 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -44,6 +44,7 @@ TESTCASES += test_mmu.tst TESTCASES += test_mul16.tst TESTCASES += test_mul32.tst TESTCASES += test_nsa.tst +TESTCASES += test_phys_mem.tst ifdef XT TESTCASES += test_pipeline.tst endif diff --git a/tests/tcg/xtensa/test_phys_mem.S b/tests/tcg/xtensa/test_phys_mem.S new file mode 100644 index 000000000000..aae0a793a718 --- /dev/null +++ b/tests/tcg/xtensa/test_phys_mem.S @@ -0,0 +1,124 @@ +#include "macros.inc" + +test_suite phys_mem + +.purgem test_init + +.macro test_init + movi a2, 0xc0000003 /* PPN */ + movi a3, 0xc0000004 /* VPN */ + wdtlb a2, a3 + witlb a2, a3 + movi a2, 0xc0000000 + wsr a2, ptevaddr +.endm + +test inst_fetch_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 + jx a2 +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 16 + assert eq, a2, a3 +test_end + +test read_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 +1: + l32i a3, a2, 0 + test_fail +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 24 + assert eq, a2, a3 +test_end + +test write_get_pte_no_phys + set_vector kernel, 2f + + movi a2, 0x20000000 +1: + s32i a3, a2, 0 + test_fail +2: + movi a2, 0x20000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 24 + assert eq, a2, a3 +test_end + +test inst_fetch_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 + jx a2 +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 14 + assert eq, a2, a3 +test_end + +test read_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 +1: + l32i a3, a2, 0 + test_fail +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 15 + assert eq, a2, a3 +test_end + +test write_no_phys + set_vector kernel, 2f + + movi a2, 0xc0000000 +1: + s32i a3, a2, 0 + test_fail +2: + movi a2, 0xc0000000 + rsr a3, excvaddr + assert eq, a2, a3 + movi a2, 1b + rsr a3, epc1 + assert eq, a2, a3 + rsr a3, exccause + movi a2, 15 + assert eq, a2, a3 +test_end + +test_suite_end