[v2,12/29] target/riscv: Convert RV64F insns to decodetree

Message ID	20181020071451.27808-13-kbastian@mail.uni-paderborn.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Sat, 20 Oct 2018 09:14:34 +0200 Message-Id: <20181020071451.27808-13-kbastian@mail.uni-paderborn.de> In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.20.70616, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 Subject: [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F insns to decodetree Precedence: list Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [v2,00/29] target/riscv: Convert to decodetree [v2,01/29] target/riscv: Move CPURISCVState pointer to DisasContext [v2,02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC [v2,03/29] target/riscv: Convert RVXI branch insns to decodetree [v2,04/29] target/riscv: Convert RVXI load/store insns to decodetree [v2,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree [v2,06/29] target/riscv: Convert RVXI fence insns to decodetree [v2,07/29] target/riscv: Convert RVXI csr insns to decodetree [v2,08/29] target/riscv: Convert RVXM insns to decodetree [v2,09/29] target/riscv: Convert RV32A insns to decodetree [v2,10/29] target/riscv: Convert RV64A insns to decodetree [v2,11/29] target/riscv: Convert RV32F insns to decodetree [v2,12/29] target/riscv: Convert RV64F insns to decodetree [v2,13/29] target/riscv: Convert RV32D insns to decodetree [v2,14/29] target/riscv: Convert RV64D insns to decodetree [v2,15/29] target/riscv: Convert RV priv insns to decodetree [v2,16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [v2,17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [v2,18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [v2,19/29] target/riscv: Remove gen_jalr() [v2,20/29] target/riscv: Remove manual decoding from gen_branch() [v2,21/29] target/riscv: Remove manual decoding from gen_load() [v2,22/29] target/riscv: Remove manual decoding from gen_store() [v2,23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions [v2,24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [v2,25/29] target/riscv: Remove shift and slt insn manual decoding [v2,26/29] target/riscv: Remove manual decoding of RV32/64M insn [v2,27/29] target/riscv: Remove gen_system() [v2,28/29] target/riscv: Remove decode_RV32_64G() [v2,29/29] target/riscv: Rename trans_arith to gen_arith

Message ID

20181020071451.27808-13-kbastian@mail.uni-paderborn.de (mailing list archive)

State

New, archived

Headers

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
	kbastian@mail.uni-paderborn.de
Date: Sat, 20 Oct 2018 09:14:34 +0200
Message-Id: <20181020071451.27808-13-kbastian@mail.uni-paderborn.de>
In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de>
References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F insns to
 decodetree
Precedence: list
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
	Alistair.Francis@wdc.com, qemu-devel@nongnu.org
Errors-To: 
 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Series

target/riscv: Convert to decodetree | expand

Commit Message

Bastian Koppelmann Oct. 20, 2018, 7:14 a.m. UTC

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v1 -> v2:
    - RISCV32 now returns false instead of raising an exception

 target/riscv/insn32.decode              |  6 +++
 target/riscv/insn_trans/trans_rvf.inc.c | 68 +++++++++++++++++++++++++
 2 files changed, 74 insertions(+)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f27bdab245..5d3d2a25ac 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -195,3 +195,9 @@  fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
 fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
 fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
 fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 3f806b8238..bd79ef96f8 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -332,3 +332,71 @@  static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a, uint32_t insn)
 
     return true;
 }
+
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+    REQUIRE_FPU;
+
+    TCGv t0 = tcg_temp_new();
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(a->rd, t0);
+    tcg_temp_free(t0);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+    REQUIRE_FPU;
+
+    TCGv t0 = tcg_temp_new();
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(a->rd, t0);
+    tcg_temp_free(t0);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+    REQUIRE_FPU;
+
+    TCGv t0 = tcg_temp_new();
+    gen_get_gpr(t0, a->rs1);
+
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+    tcg_temp_free(t0);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+    REQUIRE_FPU;
+
+    TCGv t0 = tcg_temp_new();
+    gen_get_gpr(t0, a->rs1);
+
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+    tcg_temp_free(t0);
+    return true;
+#else
+    return false;
+#endif
+}

[v2,12/29] target/riscv: Convert RV64F insns to decodetree

Commit Message

Patch