From patchwork Sat Oct 20 07:14:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 10650275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6E44914E2 for ; Sat, 20 Oct 2018 07:17:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 550192857E for ; Sat, 20 Oct 2018 07:17:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 464BC28590; Sat, 20 Oct 2018 07:17:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D8CA22857E for ; Sat, 20 Oct 2018 07:17:16 +0000 (UTC) Received: from localhost ([::1]:53969 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDlVc-0003YL-5i for patchwork-qemu-devel@patchwork.kernel.org; Sat, 20 Oct 2018 03:17:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40913) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDlTp-0002JS-MD for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDlTh-0004Ut-Lq for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:22 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:36866) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDlTh-0004IX-Ea for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:17 -0400 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 zuban) id 1gDlTW-0005D2-JY; Sat, 20 Oct 2018 09:15:06 +0200 Received: from mail.uni-paderborn.de by wormulon with queue id 2946179-5; Sat, 20 Oct 2018 07:15:05 GMT X-Envelope-From: Received: from aftr-95-222-26-83.unity-media.net ([95.222.26.83] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 telepax) id 1gDlTV-0008Eu-5Z; Sat, 20 Oct 2018 09:15:05 +0200 From: Bastian Koppelmann To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Sat, 20 Oct 2018 09:14:34 +0200 Message-Id: <20181020071451.27808-13-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.20.70616, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- v1 -> v2: - RISCV32 now returns false instead of raising an exception target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvf.inc.c | 68 +++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f27bdab245..5d3d2a25ac 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -195,3 +195,9 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 + +# *** RV64F Standard Extension (in addition to RV32F) *** +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c index 3f806b8238..bd79ef96f8 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -332,3 +332,71 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a, uint32_t insn) return true; } + +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a, uint32_t insn) +{ +#if defined(TARGET_RISCV64) + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +#else + return false; +#endif +} + +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a, uint32_t insn) +{ +#if defined(TARGET_RISCV64) + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +#else + return false; +#endif +} + +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a, uint32_t insn) +{ +#if defined(TARGET_RISCV64) + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); + + tcg_temp_free(t0); + return true; +#else + return false; +#endif +} + +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a, uint32_t insn) +{ +#if defined(TARGET_RISCV64) + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); + + tcg_temp_free(t0); + return true; +#else + return false; +#endif +}