From patchwork Sat Oct 20 07:14:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 10650307 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE4FC13A9 for ; Sat, 20 Oct 2018 07:30:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B5C0C28554 for ; Sat, 20 Oct 2018 07:30:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A680A28590; Sat, 20 Oct 2018 07:30:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3CF3528554 for ; Sat, 20 Oct 2018 07:30:30 +0000 (UTC) Received: from localhost ([::1]:54038 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDliP-0007Qt-I5 for patchwork-qemu-devel@patchwork.kernel.org; Sat, 20 Oct 2018 03:30:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDlU0-0002T0-JF for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDlTw-0004gI-3o for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:36 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:41644) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDlTt-0004Ry-QE for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:30 -0400 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 amazonia) id 1gDlTc-0005C7-7d; Sat, 20 Oct 2018 09:15:12 +0200 Received: from mail.uni-paderborn.de by tweenies with queue id 2914920-4; Sat, 20 Oct 2018 07:15:12 GMT X-Envelope-From: Received: from aftr-95-222-26-83.unity-media.net ([95.222.26.83] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 telepax) id 1gDlTc-0008Eu-3Y; Sat, 20 Oct 2018 09:15:12 +0200 From: Bastian Koppelmann To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Sat, 20 Oct 2018 09:14:43 +0200 Message-Id: <20181020071451.27808-22-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.20.70616, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- v1 -> v2: - trans_load -> gen_load - removed negative memop check target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++---------- target/riscv/translate.c | 20 -------------- 2 files changed, 21 insertions(+), 34 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 411b4bfd42..77fa66b7cd 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -129,41 +129,49 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn) return gen_branch(ctx, a, TCG_COND_GEU); } +static bool gen_load(DisasContext *ctx, arg_lb *a, int memop) +{ + TCGv t0 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); + gen_set_gpr(a->rd, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + return true; +} + static bool trans_lb(DisasContext *ctx, arg_lb *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_SB); } static bool trans_lh(DisasContext *ctx, arg_lh *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TESW); } static bool trans_lw(DisasContext *ctx, arg_lw *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TESL); } static bool trans_lbu(DisasContext *ctx, arg_lbu *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_UB); } static bool trans_lhu(DisasContext *ctx, arg_lhu *a, uint32_t insn) { - gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEUW); } static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn) { #ifdef TARGET_RISCV64 - gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEUL); #else return false; #endif @@ -172,8 +180,7 @@ static bool trans_lwu(DisasContext *ctx, arg_lwu *a, uint32_t insn) static bool trans_ld(DisasContext *ctx, arg_ld *a, uint32_t insn) { #ifdef TARGET_RISCV64 - gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEQ); #else return false; #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 52dbbd8ac8..947fb9345b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -489,26 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, ctx->base.is_jmp = DISAS_NORETURN; } -static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, - target_long imm) -{ - TCGv t0 = tcg_temp_new(); - TCGv t1 = tcg_temp_new(); - gen_get_gpr(t0, rs1); - tcg_gen_addi_tl(t0, t0, imm); - int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; - - if (memop < 0) { - gen_exception_illegal(ctx); - return; - } - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); - gen_set_gpr(rd, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); -} - static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) {