[v2,27/29] target/riscv: Remove gen_system()

Message ID	20181020071451.27808-28-kbastian@mail.uni-paderborn.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Sat, 20 Oct 2018 09:14:49 +0200 Message-Id: <20181020071451.27808-28-kbastian@mail.uni-paderborn.de> In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.20.70616, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 Subject: [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system() Precedence: list Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [v2,00/29] target/riscv: Convert to decodetree [v2,01/29] target/riscv: Move CPURISCVState pointer to DisasContext [v2,02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC [v2,03/29] target/riscv: Convert RVXI branch insns to decodetree [v2,04/29] target/riscv: Convert RVXI load/store insns to decodetree [v2,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree [v2,06/29] target/riscv: Convert RVXI fence insns to decodetree [v2,07/29] target/riscv: Convert RVXI csr insns to decodetree [v2,08/29] target/riscv: Convert RVXM insns to decodetree [v2,09/29] target/riscv: Convert RV32A insns to decodetree [v2,10/29] target/riscv: Convert RV64A insns to decodetree [v2,11/29] target/riscv: Convert RV32F insns to decodetree [v2,12/29] target/riscv: Convert RV64F insns to decodetree [v2,13/29] target/riscv: Convert RV32D insns to decodetree [v2,14/29] target/riscv: Convert RV64D insns to decodetree [v2,15/29] target/riscv: Convert RV priv insns to decodetree [v2,16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [v2,17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [v2,18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [v2,19/29] target/riscv: Remove gen_jalr() [v2,20/29] target/riscv: Remove manual decoding from gen_branch() [v2,21/29] target/riscv: Remove manual decoding from gen_load() [v2,22/29] target/riscv: Remove manual decoding from gen_store() [v2,23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions [v2,24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [v2,25/29] target/riscv: Remove shift and slt insn manual decoding [v2,26/29] target/riscv: Remove manual decoding of RV32/64M insn [v2,27/29] target/riscv: Remove gen_system() [v2,28/29] target/riscv: Remove decode_RV32_64G() [v2,29/29] target/riscv: Rename trans_arith to gen_arith

Message ID

20181020071451.27808-28-kbastian@mail.uni-paderborn.de (mailing list archive)

State

New, archived

Headers

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com,
	kbastian@mail.uni-paderborn.de
Date: Sat, 20 Oct 2018 09:14:49 +0200
Message-Id: <20181020071451.27808-28-kbastian@mail.uni-paderborn.de>
In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de>
References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system()
Precedence: list
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
	Alistair.Francis@wdc.com, qemu-devel@nongnu.org
Errors-To: 
 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Series

target/riscv: Convert to decodetree | expand

Commit Message

Bastian Koppelmann Oct. 20, 2018, 7:14 a.m. UTC

with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
 target/riscv/translate.c | 32 --------------------------------
 1 file changed, 32 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b542daf844..a3b8792a1a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -306,34 +306,6 @@  static void gen_set_rm(DisasContext *ctx, int rm)
     tcg_temp_free_i32(t0);
 }
 
-
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
-                      int rd, int rs1, int csr)
-{
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
-    switch (opc) {
-    case OPC_RISC_ECALL:
-        switch (csr) {
-        case 0x0: /* ECALL */
-            /* always generates U-level ECALL, fixed in do_interrupt handler */
-            generate_exception(ctx, RISCV_EXCP_U_ECALL);
-            tcg_gen_exit_tb(NULL, 0); /* no chaining */
-            ctx->base.is_jmp = DISAS_NORETURN;
-            break;
-        case 0x1: /* EBREAK */
-            generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
-            tcg_gen_exit_tb(NULL, 0); /* no chaining */
-            ctx->base.is_jmp = DISAS_NORETURN;
-            break;
-        default:
-            gen_exception_illegal(ctx);
-            break;
-        }
-        break;
-    }
-}
-
 #define EX_SH(amount) \
     static int32_t ex_shift_##amount(int imm) \
     {                                         \
@@ -458,10 +430,6 @@  static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
     rd = GET_RD(ctx->opcode);
 
     switch (op) {
-    case OPC_RISC_SYSTEM:
-        gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
-                   (ctx->opcode & 0xFFF00000) >> 20);
-        break;
     default:
         gen_exception_illegal(ctx);
         break;

[v2,27/29] target/riscv: Remove gen_system()

Commit Message

Patch