[v2,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree

Message ID	20181020071451.27808-6-kbastian@mail.uni-paderborn.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Sat, 20 Oct 2018 09:14:27 +0200 Message-Id: <20181020071451.27808-6-kbastian@mail.uni-paderborn.de> In-Reply-To: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> References: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.20.70616, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 Subject: [Qemu-devel] [PATCH v2 05/29] target/riscv: Convert RVXI arithmetic insns to decodetree Precedence: list Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: Convert to decodetree \| expand [v2,00/29] target/riscv: Convert to decodetree [v2,01/29] target/riscv: Move CPURISCVState pointer to DisasContext [v2,02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC [v2,03/29] target/riscv: Convert RVXI branch insns to decodetree [v2,04/29] target/riscv: Convert RVXI load/store insns to decodetree [v2,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree [v2,06/29] target/riscv: Convert RVXI fence insns to decodetree [v2,07/29] target/riscv: Convert RVXI csr insns to decodetree [v2,08/29] target/riscv: Convert RVXM insns to decodetree [v2,09/29] target/riscv: Convert RV32A insns to decodetree [v2,10/29] target/riscv: Convert RV64A insns to decodetree [v2,11/29] target/riscv: Convert RV32F insns to decodetree [v2,12/29] target/riscv: Convert RV64F insns to decodetree [v2,13/29] target/riscv: Convert RV32D insns to decodetree [v2,14/29] target/riscv: Convert RV64D insns to decodetree [v2,15/29] target/riscv: Convert RV priv insns to decodetree [v2,16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree [v2,17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree [v2,18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree [v2,19/29] target/riscv: Remove gen_jalr() [v2,20/29] target/riscv: Remove manual decoding from gen_branch() [v2,21/29] target/riscv: Remove manual decoding from gen_load() [v2,22/29] target/riscv: Remove manual decoding from gen_store() [v2,23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions [v2,24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists [v2,25/29] target/riscv: Remove shift and slt insn manual decoding [v2,26/29] target/riscv: Remove manual decoding of RV32/64M insn [v2,27/29] target/riscv: Remove gen_system() [v2,28/29] target/riscv: Remove decode_RV32_64G() [v2,29/29] target/riscv: Rename trans_arith to gen_arith

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index badd1d9216..cb7622e223 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -21,6 +21,9 @@ %rs1 15:5 %rd 7:5 +%sh6 20:6 +%sh5 20:5 + # immediates: %imm_i 20:s12 %imm_s 25:s7 7:5 @@ -30,14 +33,19 @@ # Argument sets: &branch imm rs2 rs1 +&shift shamt rs1 rd # Formats 32: +@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd @i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd @b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1 @s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1 @u .................... ..... ....... imm=%imm_u %rd @j .................... ..... ....... imm=%imm_j %rd +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u @@ -57,8 +65,36 @@ lhu ............ ..... 101 ..... 0000011 @i sb ....... ..... ..... 000 ..... 0100011 @s sh ....... ..... ..... 001 ..... 0100011 @s sw ....... ..... ..... 010 ..... 0100011 @s +addi ............ ..... 000 ..... 0010011 @i +slti ............ ..... 010 ..... 0010011 @i +sltiu ............ ..... 011 ..... 0010011 @i +xori ............ ..... 100 ..... 0010011 @i +ori ............ ..... 110 ..... 0010011 @i +andi ............ ..... 111 ..... 0010011 @i +slli 000000 ...... ..... 001 ..... 0010011 @sh6 +srli 000000 ...... ..... 101 ..... 0010011 @sh6 +srai 010000 ...... ..... 101 ..... 0010011 @sh6 +add 0000000 ..... ..... 000 ..... 0110011 @r +sub 0100000 ..... ..... 000 ..... 0110011 @r +sll 0000000 ..... ..... 001 ..... 0110011 @r +slt 0000000 ..... ..... 010 ..... 0110011 @r +sltu 0000000 ..... ..... 011 ..... 0110011 @r +xor 0000000 ..... ..... 100 ..... 0110011 @r +srl 0000000 ..... ..... 101 ..... 0110011 @r +sra 0100000 ..... ..... 101 ..... 0110011 @r +or 0000000 ..... ..... 110 ..... 0110011 @r +and 0000000 ..... ..... 111 ..... 0110011 @r # *** RV64I Base Instruction Set (in addition to RV32I) *** lwu ............ ..... 110 ..... 0000011 @i ld ............ ..... 011 ..... 0000011 @i sd ....... ..... ..... 011 ..... 0100011 @s +addiw ............ ..... 000 ..... 0011011 @i +slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 +srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 +sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 +addw 0000000 ..... ..... 000 ..... 0111011 @r +subw 0100000 ..... ..... 000 ..... 0111011 @r +sllw 0000000 ..... ..... 001 ..... 0111011 @r +srlw 0000000 ..... ..... 101 ..... 0111011 @r +sraw 0100000 ..... ..... 101 ..... 0111011 @r diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 2c8ecff76f..e5a67e64cb 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -160,3 +160,184 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn) return false; #endif } + +static bool trans_addi(DisasContext *ctx, arg_addi *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_slti(DisasContext *ctx, arg_slti *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_xori(DisasContext *ctx, arg_xori *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm); + return true; +} +static bool trans_ori(DisasContext *ctx, arg_ori *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm); + return true; +} +static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm); + return true; +} +static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt); + return true; +} + +static bool trans_srli(DisasContext *ctx, arg_srli *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt); + return true; +} + +static bool trans_srai(DisasContext *ctx, arg_srai *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400); + return true; +} + +static bool trans_add(DisasContext *ctx, arg_add *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sub(DisasContext *ctx, arg_sub *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sll(DisasContext *ctx, arg_sll *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_slt(DisasContext *ctx, arg_slt *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sltu(DisasContext *ctx, arg_sltu *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_xor(DisasContext *ctx, arg_xor *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_srl(DisasContext *ctx, arg_srl *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sra(DisasContext *ctx, arg_sra *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_or(DisasContext *ctx, arg_or *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn) +{ + gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt); + return true; +} + +static bool trans_srliw(DisasContext *ctx, arg_srliw *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt); + return true; +} + +static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a, uint32_t insn) +{ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1, + a->shamt | 0x400); + return true; +} + +static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn) +{ +#if !defined(TARGET_RISCV64) + return false; +#endif + gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn) +{ +#if !defined(TARGET_RISCV64) + return false; +#endif + gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn) +{ +#if !defined(TARGET_RISCV64) + return false; +#endif + gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_srlw(DisasContext *ctx, arg_srlw *a, uint32_t insn) +{ +#if !defined(TARGET_RISCV64) + return false; +#endif + gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sraw(DisasContext *ctx, arg_sraw *a, uint32_t insn) +{ +#if !defined(TARGET_RISCV64) + return false; +#endif + gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6b59dbb373..3e296a2627 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1701,15 +1701,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) imm = GET_IMM(ctx->opcode); switch (op) { - case OPC_RISC_ARITH_IMM: -#if defined(TARGET_RISCV64) - case OPC_RISC_ARITH_IMM_W: -#endif - if (rd == 0) { - break; /* NOP */ - } - gen_arith_imm(ctx, MASK_OP_ARITH_IMM(ctx->opcode), rd, rs1, imm); - break; case OPC_RISC_ARITH: #if defined(TARGET_RISCV64) case OPC_RISC_ARITH_W:

[v2,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree

Commit Message

Patch