diff mbox series

[PULL,3/3] Add qemu-riscv@nongnu.org as the RISC-V list

Message ID 20181030212249.7117-4-palmer@sifive.com (mailing list archive)
State New, archived
Headers show
Series [PULL,1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 | expand

Commit Message

Palmer Dabbelt Oct. 30, 2018, 9:22 p.m. UTC 
We now have a RISC-V specific QEMU development list.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index d550fd8b809c..10983bd52d64 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -244,6 +244,7 @@  M: Palmer Dabbelt <palmer@sifive.com>
 M: Alistair Francis <Alistair.Francis@wdc.com>
 M: Sagar Karandikar <sagark@eecs.berkeley.edu>
 M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
+L: qemu-riscv@nongnu.org
 S: Maintained
 F: target/riscv/
 F: hw/riscv/