From patchwork Fri Nov 9 19:19:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10676507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2AEB213BF for ; Fri, 9 Nov 2018 19:22:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1BD892F0CD for ; Fri, 9 Nov 2018 19:22:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0FD642F0D0; Fri, 9 Nov 2018 19:22:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A8F9C2F0CD for ; Fri, 9 Nov 2018 19:22:27 +0000 (UTC) Received: from localhost ([::1]:35660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gLCMM-0005ZK-UT for patchwork-qemu-devel@patchwork.kernel.org; Fri, 09 Nov 2018 14:22:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42568) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gLCKX-0002Xl-Jv for qemu-devel@nongnu.org; Fri, 09 Nov 2018 14:20:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gLCKT-0001lx-Rc for qemu-devel@nongnu.org; Fri, 09 Nov 2018 14:20:33 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:39119) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gLCKO-0001Zd-F4 for qemu-devel@nongnu.org; Fri, 09 Nov 2018 14:20:24 -0500 Received: by mail-pl1-x641.google.com with SMTP id b5-v6so1356209pla.6 for ; Fri, 09 Nov 2018 11:20:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=PIrU5TXJVpuoBGAJ5WMK/veUeOQU9F1BWjTRGr4Sy5g=; b=jXnuX2CPKDNxIysm0gbm8YRY3FK9m09I+mS3VOoY0G+Ox8tscZx8ZGtGK9IjwzbogD rjo8w4fe8sbjUNKgpOcElki0XZu06hzUckj5eCe2OKtquU5x/38R9qd/cQXd1AsS4OI5 WJUtuY1O6a2i5wf5ykhogtbWuDsPkvp8PcV0xcMr8kB1wAlme96SHLL01joJ+CI4Tae4 TLDwgJb9Sf0UFiDCuG7FazWWNPJ5oDM6Aa3q/ki+oG3gq/vH/7UUtys8KcKx5aanJogF 2IuLxg0mALuCHMi1HQuNMMBzWi/Y51MM+vyh4iXv6KF0JE15WYwNNVp6uiCSf3FoWWOx edJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=PIrU5TXJVpuoBGAJ5WMK/veUeOQU9F1BWjTRGr4Sy5g=; b=gDbWW6xvo3qWMaiZ//Dinn7FwOUvuMlwLaRaH2hPWgEZkw0UJ4C57+gVQr38TDlZ0+ B96vKLnB0BAHwOWL4NrRfER7ov8ETfwiERjBVU1X4jVLhEZX4mS1EYjz6FYSWk1PechQ 7Hl+C0k1oKOqzmREpK+7WmfY9aN3JR3UFHex7PxxRAp0Q4lA5DJTXI/F7JOeb8Y6E29Z V48jGjdimSThQ+AEcwdTry8sluIvj2FGdDtK32VqfiliVVl4odlv+Rj+liRhzqHss+i4 CSfSo+frzbnruG+GGlg3nzhZg9cTR0zaAh6YEoKIxQGpIKQBoSnsDixCxd96GWy9s+z5 KhJg== X-Gm-Message-State: AGRZ1gIiNeQaUc5C2jxmgkex4ufksfBzeb6eGpWjhueAZTE/920wYjpN JT7+mZsO+qF/3JmZI3IdK6sa7SDOz0Y= X-Google-Smtp-Source: AJdET5ceQdrcnYK9baihWebpAa9noCzoIRvBslNwCtMFOy2ZiN242ZUTiYSD5uTqRCaHXeJizol5ZA== X-Received: by 2002:a17:902:15a8:: with SMTP id m37-v6mr10064383pla.256.1541791216759; Fri, 09 Nov 2018 11:20:16 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id f6-v6sm10355007pfg.128.2018.11.09.11.20.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Nov 2018 11:20:16 -0800 (PST) Date: Fri, 9 Nov 2018 11:19:34 -0800 Message-Id: <20181109191933.6641-2-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181109191933.6641-1-palmer@sifive.com> References: <20181109191933.6641-1-palmer@sifive.com> From: Palmer Dabbelt To: qemu-riscv@nongnu.org, richard.henderson@linaro.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH for 3.1] RISC-V: Respect fences for user-only emulators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Our current fence implementation ignores fences for the user-only configurations. This is incorrect but unlikely to manifest: it requires multi-threaded user-only code that takes advantage of the weakness in the host's memory model and can be inlined by TCG. This patch simply treats fences the same way for all our emulators. I've given it to testing as I don't want to construct a test that would actually trigger the failure. Our fence implementation has an additional deficiency where we map all RISC-V fences to full fences. Now that we have a formal memory model for RISC-V we can start to take advantage of the strength bits on our fence instructions. This requires a bit more though, so I'm going to split it out because the implementation is still correct without taking advantage of these weaker fences. Thanks to Richard Henderson for pointing out both of the issues. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d1471d..624d1c679a84 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1766,7 +1766,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) GET_RM(ctx->opcode)); break; case OPC_RISC_FENCE: -#ifndef CONFIG_USER_ONLY if (ctx->opcode & 0x1000) { /* FENCE_I is a no-op in QEMU, * however we need to end the translation block */ @@ -1777,7 +1776,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) /* FENCE is a full memory barrier. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); } -#endif break; case OPC_RISC_SYSTEM: gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,