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X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PULL 2/4] target/riscv: Fix FCLASS_D being treated as RV64 only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Bastian Koppelmann Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d1471d..5359088e24bc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1237,13 +1237,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); break; -#if defined(TARGET_RISCV64) case OPC_RISC_FMV_X_D: /* also OPC_RISC_FCLASS_D */ switch (rm) { +#if defined(TARGET_RISCV64) case 0: /* FMV */ gen_set_gpr(rd, cpu_fpr[rs1]); break; +#endif case 1: t0 = tcg_temp_new(); gen_helper_fclass_d(t0, cpu_fpr[rs1]); @@ -1255,6 +1256,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } break; +#if defined(TARGET_RISCV64) case OPC_RISC_FMV_D_X: t0 = tcg_temp_new(); gen_get_gpr(t0, rs1);