From patchwork Fri Nov 16 21:30:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10687047 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 379AF14D6 for ; Fri, 16 Nov 2018 21:35:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D56A2D1DF for ; Fri, 16 Nov 2018 21:35:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0DF612D54A; Fri, 16 Nov 2018 21:35:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DDD072D1DF for ; Fri, 16 Nov 2018 21:35:05 +0000 (UTC) Received: from localhost ([::1]:47074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gNllZ-0003SC-4D for patchwork-qemu-devel@patchwork.kernel.org; Fri, 16 Nov 2018 16:35:05 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59700) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gNlhn-0000Mb-0V for qemu-devel@nongnu.org; Fri, 16 Nov 2018 16:31:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gNlhm-0001jZ-4Z for qemu-devel@nongnu.org; Fri, 16 Nov 2018 16:31:10 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:41631) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gNlhi-0001i7-Nx for qemu-devel@nongnu.org; Fri, 16 Nov 2018 16:31:07 -0500 Received: by mail-pl1-x643.google.com with SMTP id u6so836221plm.8 for ; Fri, 16 Nov 2018 13:31:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=jiJQ+JOIMV0I2GJ3MV1g+OOMPgoMF7Rval6G4QIiJEo=; b=fLjdESVhv2xwTT21MeffYpIh0HMhB3SFnlF7rgYLDWMBY6hFo3eibRHJIUQEVcUZuZ eB2x/xXykGAkS3rb8eON9G8Ln1yte39VFHUu5qqBCdN4cd2Jv17ds73SVThOQd75CR/7 PCVnR1qGraKHrhvFNcUeYCFby+BcHl6KQtoXqNW0f5O3hV9AOjBjmgVmZQmN9Y+r9PWl buItHvdU2KrzYZC2n5OyREdxZupTkgAFYGDjt37xR0GXyaYjytPz4uyxrEIRCrA0k4j3 lcdTUTjmllZ/CV+pR7LuX3Atqf3hD7zsDjcaHZ0EptfXAYqqoi5bILPFZfe4nZelYAbi hcag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=jiJQ+JOIMV0I2GJ3MV1g+OOMPgoMF7Rval6G4QIiJEo=; b=lOz1HJoGjx+rlhO4D8W+Z0k9cAjLgxV/8fRwFWB0Y+G45VRkoKe4wX0D8gsZBaEcN3 vdnj2+ptU6NSPgbzsSlclLLj3wrcRyTqel2ew///qaM33JGM6kOwZxiFirTEkkZ38Zf4 6ebn29+P+stXl6H2GFAlIq5BliSzvbNRmtQSmqCD1934Z5WuG+i8UlU55UFEddJZ0/Wz T1IpIV19qhDgtZvM4ANj4wWPbqJ0OLXhxRZwOs/BV9qN6fHWY8QTMJSHXqYV9rA9d92L kpmq/KSxD+918NV1PDD7pQ0Gu9APVCetgCuK7rNwbnIsuhf1Oe2+rcO3qm7yHiUky85f wyiw== X-Gm-Message-State: AGRZ1gIrwn5wQQCHyoTISeq+7GvVQyqXaCMDW/NY4D8T8sD7tqOplqkR VB6AYgTE/TNADBXjU5Iaetz3ubvRLGdxPQ== X-Google-Smtp-Source: AJdET5eiq0GVlZ+LqLj1BVw65NbTf4O+nPvGB8kWWoSiL+XcBAolYxAVHSU713GwVIIK4MKF2wYhgw== X-Received: by 2002:a17:902:930b:: with SMTP id bc11mr8729361plb.17.1542403862612; Fri, 16 Nov 2018 13:31:02 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id c13sm11588314pfo.121.2018.11.16.13.31.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Nov 2018 13:31:01 -0800 (PST) Date: Fri, 16 Nov 2018 13:30:44 -0800 Message-Id: <20181116213045.19825-5-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181116213045.19825-1-palmer@sifive.com> References: <20181116213045.19825-1-palmer@sifive.com> From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PULL 4/4] RISC-V: Respect fences for user-only emulators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Our current fence implementation ignores fences for the user-only configurations. This is incorrect but unlikely to manifest: it requires multi-threaded user-only code that takes advantage of the weakness in the host's memory model and can be inlined by TCG. This patch simply treats fences the same way for all our emulators. I've given it to testing as I don't want to construct a test that would actually trigger the failure. Our fence implementation has an additional deficiency where we map all RISC-V fences to full fences. Now that we have a formal memory model for RISC-V we can start to take advantage of the strength bits on our fence instructions. This requires a bit more though, so I'm going to split it out because the implementation is still correct without taking advantage of these weaker fences. Thanks to Richard Henderson for pointing out both of the issues. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f44eb9c41b48..312bf298b3c2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1776,7 +1776,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) GET_RM(ctx->opcode)); break; case OPC_RISC_FENCE: -#ifndef CONFIG_USER_ONLY if (ctx->opcode & 0x1000) { /* FENCE_I is a no-op in QEMU, * however we need to end the translation block */ @@ -1787,7 +1786,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) /* FENCE is a full memory barrier. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); } -#endif break; case OPC_RISC_SYSTEM: gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,