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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB5228; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:0; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 8fH0bwAJH1OKzw8fa9+R/UpvnEVv4ETi0z+P2ClxtluUmANqDRverbAK93jkJzWiCgl5Ultk58juIn4+Z/9SbmlAkFGY2c7MLzJ+BuIv6WNYFwNDuTNDvMTg178BmVF+XHqQldG1aOidw47VmVFkI7Xhbje7ra0kBvaDJ9GhaA1P6abXcxvTpQyljWHPNIJLZr2dZUAsdxr9WKwpmmInwVSUPvS4QIvZUL06EjAJDPuREsqJCRp+3Shai0rJhWjN9q/4IW0KT8MRZ+u54HxOjaxeimAccbTQe31wPw+iCw4U/SQfVxmJ7f+gvcxSBOfoqpc8spgqJL4tOn47A1ow1KuHtpnrnGaHB5to4cQP4kU= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: dcecc0ab-b07e-4a5b-eca2-08d64f2edba9 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Nov 2018 21:26:39.4440 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB5228 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.74.133 Subject: [Qemu-devel] [PATCH v8 06/13] target/arm: Implement PMOVSSET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0aff261528..71be6fb578 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1342,6 +1342,13 @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, env->cp15.c9_pmovsr &= ~value; } +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= pmu_counter_mask(env); + env->cp15.c9_pmovsr |= value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1709,6 +1716,24 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo pmovsset_cp_reginfo[] = { + /* PMOVSSET is not implemented in v7 before v7ve */ + { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsset_write, + .raw_writefn = raw_write }, + REGINFO_SENTINEL +}; + static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5191,6 +5216,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, pmovsset_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle