From patchwork Wed Dec 5 13:43:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Lindsay X-Patchwork-Id: 10714219 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8E8C91057 for ; Wed, 5 Dec 2018 13:46:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C4472CD4D for ; Wed, 5 Dec 2018 13:46:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6D4DC2CDA0; Wed, 5 Dec 2018 13:46:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 85A332CD4D for ; Wed, 5 Dec 2018 13:46:51 +0000 (UTC) Received: from localhost ([::1]:34605 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXVq-0001zs-5A for patchwork-qemu-devel@patchwork.kernel.org; Wed, 05 Dec 2018 08:46:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXSc-0007aJ-Ki for qemu-devel@nongnu.org; Wed, 05 Dec 2018 08:43:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUXSb-0004nE-7F for qemu-devel@nongnu.org; Wed, 05 Dec 2018 08:43:30 -0500 Received: from mail-eopbgr700125.outbound.protection.outlook.com ([40.107.70.125]:10909 helo=NAM04-SN1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUXSV-0004aK-VA; Wed, 05 Dec 2018 08:43:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amperemail.onmicrosoft.com; s=selector1-os-amperecomputing-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H+4A+wFBmuvVssaHZTtbIypoPXD7UJkxaa5EwTasED0=; b=obtcDdKRJgNJ9tpbWing1h5qpXo5YA+Tvy/rDViWOok8t9xzrbzpCw4JQZaFnqkzdBORQ8RggwbdAXGCQG4gS3p4MIidjNrGqPB9hXo0nTYFTBaakJmzdiUEsVn8j0ihtOm6F7Rxd4oa2wDSL8mSInXL3UOLRwcT4RGGM5y1Tq0= Received: from DM6PR01MB4825.prod.exchangelabs.com (20.177.218.222) by DM6PR01MB4700.prod.exchangelabs.com (20.177.217.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1382.22; Wed, 5 Dec 2018 13:43:20 +0000 Received: from DM6PR01MB4825.prod.exchangelabs.com ([fe80::9c7c:27c7:4cb7:f820]) by DM6PR01MB4825.prod.exchangelabs.com ([fe80::9c7c:27c7:4cb7:f820%2]) with mapi id 15.20.1404.016; Wed, 5 Dec 2018 13:43:20 +0000 From: Aaron Lindsay To: "qemu-arm@nongnu.org" , Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite , Richard Henderson Thread-Topic: [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Thread-Index: AQHUjKB6UrXtXqjnS0mon7f8aIsO3w== Date: Wed, 5 Dec 2018 13:43:18 +0000 Message-ID: <20181205134243.4791-5-aaron@os.amperecomputing.com> References: <20181205134243.4791-1-aaron@os.amperecomputing.com> In-Reply-To: <20181205134243.4791-1-aaron@os.amperecomputing.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BN6PR12CA0032.namprd12.prod.outlook.com (2603:10b6:405:70::18) To DM6PR01MB4825.prod.exchangelabs.com (2603:10b6:5:6b::30) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aaron@os.amperecomputing.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [216.85.170.155] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DM6PR01MB4700; 6:F+JCOJyAyjSaiGYgEQ81XvRa2D8Ic6CtDlxQp6fkZ+1EUSSxjMABmUzXk99qF9doXFRlBwfbDCotcsAKA6zGapm+hcLvNxhfg61Vk2hgaS0X3cLhR9fUtAm++9D7rgq1hvZuPjDvzFmnq6g1serWufoehZPAodN7P2YCUEeRwJ046+XjuhgDVQRooxuhNZBT7vpXVbK7ZIqIBFbVt1VqlPTB8ilMEeWf9zT0qeMQ2sX7o1y2lWpB+27is2KfUKpn9wn69nIc7z4i+WAz37vVFFv7sXDqSU79jWSk2zmuSnEgkUwOZzRcCKM6h9d4Ornb0YsDyR8+6LluUflwiBKx4k1/aDx0gCOVgXS81JDGU7Yn+QCR5IF/VHfWnp7AgonW5rnzALSI4ezfJx5n4jD4zB6yht1LU8cKhyEyLT2oL3SuHPKmzwgOrqzr/TNQMFcxxa1mNMc4EKYveMffQH1gvw==; 5:WJGUNCK9/PAyhQ7wCIMFJqH/LN1gjL+6OOvN7Mx2+MRp2PsqeEc+WaDw+Na0+8AXOmN8gCJTdmEfUuPki3ROdM+e2rCsqvZZ6oyHr/MbO8FDKUWWMZamu/vWq53MAXE3i+aePyphhWNxyeQkQwIapuF/FsYHkjtvllrXtyBhWwg=; 7:8fngC6YvX5uUvgVEz/q3gbsLU6rX+nxZyZ+cgIVRM2FiUvJqpiMKkvW6DtrIOOuWdBohFhdd97b0TGtE/e0ryFTOmmDYTue0RcqlmUr/U+AqTfP7J9+2HWKbz4WOGHY+81kcao3X5qA2uf0Z69LGfA== x-ms-office365-filtering-correlation-id: 7e706ad5-ff2a-465f-ce69-08d65ab79d1e x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390098)(7020095)(4652040)(8989299)(5600074)(711020)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:DM6PR01MB4700; x-ms-traffictypediagnostic: DM6PR01MB4700: x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(3231455)(999002)(944501520)(52105112)(93006095)(93001095)(3002001)(148016)(149066)(150057)(6041310)(20161123558120)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123564045)(201708071742011)(7699051)(76991095); SRVR:DM6PR01MB4700; BCL:0; PCL:0; RULEID:; SRVR:DM6PR01MB4700; x-forefront-prvs: 08770259B4 x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(396003)(366004)(136003)(376002)(346002)(39850400004)(189003)(199004)(386003)(2906002)(6506007)(2616005)(476003)(97736004)(446003)(11346002)(486006)(102836004)(14454004)(26005)(99286004)(106356001)(3846002)(186003)(6116002)(1076002)(6436002)(81166006)(81156014)(8936002)(54906003)(316002)(575784001)(86362001)(68736007)(6486002)(25786009)(8676002)(7736002)(7416002)(110136005)(305945005)(2501003)(71190400001)(71200400001)(4326008)(39060400002)(76176011)(66066001)(52116002)(53936002)(5660300001)(256004)(14444005)(478600001)(6512007)(105586002); DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB4700; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:0; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 3Dcz9YuejQNLldcu/zX8dXw/18YawFVcDA2PQMquvzNz433bg0FwNvfOLFUgJnW4lulJ2wpEZfjpbFPh+QHSc+aZEPwZ2VAodlzGP+4INId9SuH4VJ5gqAFlLievL6NGVBrH1uthY1eTsWN+Ob0nGkCrgYbN6v+BmDYUS/uaPt0Dpgd8K2XaKauz2QxCSzXQ0+bfSGSHFh1l9chCCKuYhs/EA1Ht3LCdTkzz1Vj6pJd7Cf4Q8jNECwc+ArwSGrB3aj618IBY25euhVmoVrOMU1fbqol4xrIm6pur7DDkrVGIy4zmaMDLie/ULmusndxoVv9DriLJni3LoneqmzsdPFnBKoUbG+Tc/7QtbMG2XAA= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7e706ad5-ff2a-465f-ce69-08d65ab79d1e X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Dec 2018 13:43:18.3091 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB4700 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.70.125 Subject: [Qemu-devel] [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Spradling , Digant Desai , "qemu-devel@nongnu.org" , Aaron Lindsay , Aaron Lindsay Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only return 'true' if the specified counter is enabled and neither prohibited or filtered. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 ++ target/arm/cpu.h | 10 ++++- target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 101 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60411f6bfe..f7bad04f60 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1020,6 +1020,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &= ~0xf00; + } else if (!kvm_enabled()) { + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } if (!arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 61ac458627..627e5c1995 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -987,6 +987,12 @@ void pmccntr_op_finish(CPUARMState *env); void pmu_op_start(CPUARMState *env); void pmu_op_finish(CPUARMState *env); +/** + * Functions to register as EL change hooks for PMU mode filtering + */ +void pmu_pre_el_change(ARMCPU *cpu, void *ignored); +void pmu_post_el_change(ARMCPU *cpu, void *ignored); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those @@ -1048,7 +1054,8 @@ void pmu_op_finish(CPUARMState *env); #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) -#define MDCR_SPME (1U << 17) +#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ +#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ #define MDCR_SDD (1U << 16) #define MDCR_SPD (3U << 14) #define MDCR_TDRA (1U << 11) @@ -1058,6 +1065,7 @@ void pmu_op_finish(CPUARMState *env); #define MDCR_HPME (1U << 7) #define MDCR_TPM (1U << 6) #define MDCR_TPMCR (1U << 5) +#define MDCR_HPMN (0x1fU) /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) diff --git a/target/arm/helper.c b/target/arm/helper.c index 71a5c71e0a..ddb47813d2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -976,10 +976,24 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRE 0x1 +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x0000ffff +#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ + PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ + PMXEVTYPER_M | PMXEVTYPER_MT | \ + PMXEVTYPER_EVTCOUNT) + static inline uint32_t pmu_num_counters(CPUARMState *env) { return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; @@ -1075,16 +1089,66 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env, return pmreg_access(env, ri, isread); } -static inline bool arm_ccnt_enabled(CPUARMState *env) +/* Returns true if the counter (pass 31 for PMCCNTR) should count events using + * the current EL, security state, and register configuration. + */ +static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) { - /* This does not support checking PMCCFILTR_EL0 register */ + uint64_t filter; + bool e, p, u, nsk, nsu, nsh, m; + bool enabled, prohibited, filtered; + bool secure = arm_is_secure(env); + int el = arm_current_el(env); + uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; - if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31))) { - return false; + if (!arm_feature(env, ARM_FEATURE_EL2) || + (counter < hpmn || counter == 31)) { + e = env->cp15.c9_pmcr & PMCRE; + } else { + e = env->cp15.mdcr_el2 & MDCR_HPME; } + enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); - return true; + if (!secure) { + if (el == 2 && (counter < hpmn || counter == 31)) { + prohibited = env->cp15.mdcr_el2 & MDCR_HPMD; + } else { + prohibited = false; + } + } else { + prohibited = arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.mdcr_el3 & MDCR_SPME); + } + + if (prohibited && counter == 31) { + prohibited = env->cp15.c9_pmcr & PMCRDP; + } + + /* TODO Remove assert, set filter to correct PMEVTYPER */ + assert(counter == 31); + filter = env->cp15.pmccfiltr_el0; + + p = filter & PMXEVTYPER_P; + u = filter & PMXEVTYPER_U; + nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); + nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); + nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); + m = arm_el_is_aa64(env, 1) && + arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); + + if (el == 0) { + filtered = secure ? u : u != nsu; + } else if (el == 1) { + filtered = secure ? p : p != nsk; + } else if (el == 2) { + filtered = !nsh; + } else { /* EL3 */ + filtered = m != p; + } + + return enabled && !prohibited && !filtered; } + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1097,7 +1161,7 @@ void pmccntr_op_start(CPUARMState *env) cycles = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - if (arm_ccnt_enabled(env)) { + if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles = cycles; if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -1116,7 +1180,7 @@ void pmccntr_op_start(CPUARMState *env) */ void pmccntr_op_finish(CPUARMState *env) { - if (arm_ccnt_enabled(env)) { + if (pmu_counter_enabled(env, 31)) { uint64_t prev_cycles = env->cp15.c15_ccnt_delta; if (env->cp15.c9_pmcr & PMCRD) { @@ -1138,6 +1202,16 @@ void pmu_op_finish(CPUARMState *env) pmccntr_op_finish(env); } +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_start(&cpu->env); +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_finish(&cpu->env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1209,6 +1283,14 @@ void pmu_op_finish(CPUARMState *env) { } +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ +} + #endif static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,