[PR,RFC] RISC-V Changes for 3.2, Part 1

Pull-request

git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-3.2-part1

Message

Palmer Dabbelt Dec. 21, 2018, 4:02 p.m. UTC

The following changes since commit b72566a4ffaddbc0c0c1f6f5ee91b42ab13ff429:

  Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-19 15:31:02 +0000)

are available in the Git repository at:

  git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-3.2-part1

for you to fetch changes up to 7b91ae7d7944056c5e8045342e4039e978e43c82:

  MAINTAINERS: Mark RISC-V as Supported (2018-12-21 07:57:15 -0800)

----------------------------------------------------------------
RISC-V Changes for 3.2, Part 1

This pull request contains the first set of RISC-V patches I'd like to
target for the 3.2 development cycle.  It's really just a collection of
bug fixes with one major new feature: PCIe can now be attached to RISC-V
guests.

This has passed my usual test of booting the latest Linux RC into a
Fedora disk image on the virt machine.

----------------------------------------------------------------
Alistair Francis (4):
      hw/riscv/virt: Increase the number of interrupts
      hw/riscv/virt: Adjust memory layout spacing
      hw/riscv/virt: Connect the gpex PCIe
      riscv: Enable VGA and PCIE_VGA

Anup Patel (3):
      sifive_u: Add clock DT node for GEM ethernet
      sifive_u: Set 'clock-frequency' DT property for SiFive UART
      target/riscv/pmp.c: Fix pmp_decode_napot()

Mao Zhongyi (1):
      riscv/cpu: use device_class_set_parent_realize

Michael Clark (4):
      RISC-V: Add hartid and \n to interrupt logging
      RISC-V: Fix CLINT timecmp low 32-bit writes
      RISC-V: Fix PLIC pending bitfield reads
      RISC-V: Enable second UART on sifive_e and sifive_u

Nathaniel Graff (1):
      sifive_uart: Implement interrupt pending register

Palmer Dabbelt (1):
      MAINTAINERS: Mark RISC-V as Supported

 MAINTAINERS                         |   2 +-
 default-configs/riscv32-softmmu.mak |   8 +-
 default-configs/riscv64-softmmu.mak |   8 +-
 hw/riscv/sifive_clint.c             |   8 +-
 hw/riscv/sifive_e.c                 |   5 +-
 hw/riscv/sifive_plic.c              |   2 +-
 hw/riscv/sifive_u.c                 |  25 +++++-
 hw/riscv/sifive_uart.c              |  24 ++++--
 hw/riscv/virt.c                     | 147 +++++++++++++++++++++++++++++++++---
 include/hw/riscv/sifive_u.h         |   3 +-
 include/hw/riscv/sifive_uart.h      |   3 +
 include/hw/riscv/virt.h             |  15 +++-
 target/riscv/cpu.c                  |   4 +-
 target/riscv/cpu_helper.c           |  18 +++--
 target/riscv/pmp.c                  |   2 +-
 15 files changed, 231 insertions(+), 43 deletions(-)