[PULL,14/14] MAINTAINERS: Mark RISC-V as Supported

Message ID	20181226172005.26990-15-palmer@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> Date: Wed, 26 Dec 2018 09:20:05 -0800 Message-Id: <20181226172005.26990-15-palmer@sifive.com> In-Reply-To: <20181226172005.26990-1-palmer@sifive.com> References: <20181226172005.26990-1-palmer@sifive.com> From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported Precedence: list Cc: Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	[PULL] RISC-V Changes for 3.2, Part 1 \| expand [PULL] RISC-V Changes for 3.2, Part 1 [PULL,02/14] hw/riscv/virt: Adjust memory layout spacing [PULL,03/14] hw/riscv/virt: Connect the gpex PCIe [PULL,04/14] riscv: Enable VGA and PCIE_VGA [PULL,05/14] sifive_u: Add clock DT node for GEM ethernet [PULL,06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART [PULL,07/14] RISC-V: Add hartid and \n to interrupt logging [PULL,08/14] RISC-V: Fix CLINT timecmp low 32-bit writes [PULL,09/14] RISC-V: Fix PLIC pending bitfield reads [PULL,10/14] RISC-V: Enable second UART on sifive_e and sifive_u [PULL,11/14] sifive_uart: Implement interrupt pending register [PULL,12/14] target/riscv/pmp.c: Fix pmp_decode_napot() [PULL,13/14] riscv/cpu: use device_class_set_parent_realize [PULL,14/14] MAINTAINERS: Mark RISC-V as Supported

Message ID

20181226172005.26990-15-palmer@sifive.com (mailing list archive)

State

New, archived

Headers

Date: Wed, 26 Dec 2018 09:20:05 -0800
Message-Id: <20181226172005.26990-15-palmer@sifive.com>
In-Reply-To: <20181226172005.26990-1-palmer@sifive.com>
References: <20181226172005.26990-1-palmer@sifive.com>
From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Subject: [Qemu-devel] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported
Precedence: list
Cc: Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Errors-To: 
 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Series

[PULL] RISC-V Changes for 3.2, Part 1 | expand

Commit Message

Palmer Dabbelt Dec. 26, 2018, 5:20 p.m. UTC

There's at least two of us that are paid to work on this.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index d676c73f8840..317eff6cec4d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -262,7 +262,7 @@  M: Alistair Francis <Alistair.Francis@wdc.com>
 M: Sagar Karandikar <sagark@eecs.berkeley.edu>
 M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 L: qemu-riscv@nongnu.org
-S: Maintained
+S: Supported
 F: target/riscv/
 F: hw/riscv/
 F: include/hw/riscv/

[PULL,14/14] MAINTAINERS: Mark RISC-V as Supported

Commit Message

Patch