From patchwork Wed Dec 26 17:19:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 10743245 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 738AA6C2 for ; Wed, 26 Dec 2018 17:27:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56360287AC for ; Wed, 26 Dec 2018 17:27:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 488E5287B1; Wed, 26 Dec 2018 17:27:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5ED46287AD for ; Wed, 26 Dec 2018 17:27:03 +0000 (UTC) Received: from localhost ([127.0.0.1]:47452 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gcCxS-0003qL-GX for patchwork-qemu-devel@patchwork.kernel.org; Wed, 26 Dec 2018 12:27:02 -0500 Received: from eggs.gnu.org ([208.118.235.92]:47943) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gcCrF-000474-UK for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gcCrC-0007pd-Sb for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:35 -0500 Received: from mail-qk1-x743.google.com ([2607:f8b0:4864:20::743]:40920) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gcCrC-0007m4-2H for qemu-devel@nongnu.org; Wed, 26 Dec 2018 12:20:34 -0500 Received: by mail-qk1-x743.google.com with SMTP id y16so9621714qki.7 for ; Wed, 26 Dec 2018 09:20:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:cc:from:to; bh=WHGAQUfOGf/lF2aQbiDJ1O5xra2r7l4uqRWZE5qJgIs=; b=jh9Pk4XjZBvkRVzqBGxwtDTMi7TiqBV5bXoLhGvlrPwFEGzLgTthfR1RhrxG1BYKRF d+u9aagpylBap8s6gdG9h2L636vJB20UgqjBmXzfnktCoXbqVGyX/1RKb5aEpNpiP7PV C5oRYpEmxKr4ox+amGbaFLsL5yuh/bdneHlUwrjeqyIXXp2tE1cEs6anVhf+ImUPASHq DPLTKz1cOBwx8HSkgLWQqR4EYHf62Psz+Z43fGedFk7PvQJ7gkzVRazR4aBHhXGgZsTM F3UPvpmNsc6SeJnTGX4Ix7ZGJ3hI6uOq2RS1JwhD8N8BKmIoJ5H2t4k3qSumtHf2MBnU wcuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :cc:from:to; bh=WHGAQUfOGf/lF2aQbiDJ1O5xra2r7l4uqRWZE5qJgIs=; b=hAXkgwYfLHhJvOGDuD9JAlpgzA9pYb8jqqpHSludURcO2XaD7CvdqxFo0gHfSfyRm2 BmRvl//tk8+LxlCukPliiC39mvSe896+J+PRtinZnG6aMpHIuKBWhCm94ZQ0ocXW+0pq b2xqshWIHXHwUdFKz/9b+pN8q5xjeDPm+IWFfqqXIRULbEKXpV8qtzNxysinLkOqoRcG fR3demlY14ZC4sAJ1Eu9yeZicnFn4M0BOhkL6DlmE54+k1GWtSpGTkOogq27bzS8QFZg KEVq+GWCw8PQ8fdKVIiWFoinHV1i0VGFEQxfe5KWAYtPhMEZBaBllVZhkWi0P8MC/skN yMnA== X-Gm-Message-State: AJcUukcWSVkpDECvU8nFs6eMOegO4lXCFKePKrmReod4cwzu5FV+JXm2 39W1RvMZdl3/Jwrky5XwPJ28Ug== X-Google-Smtp-Source: ALg8bN4svfrDAlxYKl+NsPTyCmuxbmm7ZDU/jTqowIEYq0ozONw5YCu6tfBmpNzO62A/WRjyeN6owQ== X-Received: by 2002:a37:7d85:: with SMTP id y127mr19100936qkc.302.1545844828127; Wed, 26 Dec 2018 09:20:28 -0800 (PST) Received: from localhost ([2601:182:c980:96c:8dd:4488:90b1:59d1]) by smtp.gmail.com with ESMTPSA id b17sm12614931qkj.69.2018.12.26.09.20.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Dec 2018 09:20:27 -0800 (PST) Date: Wed, 26 Dec 2018 09:19:59 -0800 Message-Id: <20181226172005.26990-9-palmer@sifive.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181226172005.26990-1-palmer@sifive.com> References: <20181226172005.26990-1-palmer@sifive.com> From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::743 Subject: [Qemu-devel] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Michael Clark A missing shift made updates to the low order bits of timecmp erroneously copy the old low order bits into the high order bits of the 64-bit timecmp register. Add the missing shift and rename timecmp local variables to timecmp_hi and timecmp_lo. This bug didn't show up as the low order bits are usually written first followed by the high order bits meaning the high order bits contained an invalid value between the timecmp_lo and timecmp_hi update. Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Alistair Francis Co-Authored-by: Johannes Haring Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_clint.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 0d2fd52487e6..d4c159e93736 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -146,15 +146,15 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, error_report("clint: invalid timecmp hartid: %zu", hartid); } else if ((addr & 0x7) == 0) { /* timecmp_lo */ - uint64_t timecmp = env->timecmp; + uint64_t timecmp_hi = env->timecmp >> 32; sifive_clint_write_timecmp(RISCV_CPU(cpu), - timecmp << 32 | (value & 0xFFFFFFFF)); + timecmp_hi << 32 | (value & 0xFFFFFFFF)); return; } else if ((addr & 0x7) == 4) { /* timecmp_hi */ - uint64_t timecmp = env->timecmp; + uint64_t timecmp_lo = env->timecmp; sifive_clint_write_timecmp(RISCV_CPU(cpu), - value << 32 | (timecmp & 0xFFFFFFFF)); + value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { error_report("clint: invalid timecmp write: %08x", (uint32_t)addr); }