| Message ID | 20190104142812.20444-3-edgar.iglesias@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/microblaze: Add properties to enable exceptions on failed bus accesses | expand |
On Fri, Jan 4, 2019 at 6:28 AM Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Add MicroBlaze CPU properties to enable exceptions on failed > bus accesses. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/microblaze/cpu.c | 12 +++++++++++- > target/microblaze/cpu.h | 2 ++ > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c > index 49876b19b3..5596cd5485 100644 > --- a/target/microblaze/cpu.c > +++ b/target/microblaze/cpu.c > @@ -202,7 +202,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | > (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | > (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | > - (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); > + (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | > + (cpu->cfg.dopb_bus_exception ? > + PVR2_DOPB_BUS_EXC_MASK : 0) | > + (cpu->cfg.iopb_bus_exception ? > + PVR2_IOPB_BUS_EXC_MASK : 0); > > env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? > PVR5_DCACHE_WRITEBACK_MASK : 0; > @@ -265,6 +269,12 @@ static Property mb_properties[] = { > DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, > false), > DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), > + /* Enables bus exceptions on failed data accesses (load/stores). */ > + DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU, > + cfg.dopb_bus_exception, false), > + /* Enables bus exceptions on failed instruction fetches. */ > + DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, > + cfg.iopb_bus_exception, false), > DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), > DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), > DEFINE_PROP_END_OF_LIST(), > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index 03ca91007d..792bbc97c7 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -308,6 +308,8 @@ struct MicroBlazeCPU { > bool use_mmu; > bool dcache_writeback; > bool endi; > + bool dopb_bus_exception; > + bool iopb_bus_exception; > char *version; > uint8_t pvr; > } cfg; > -- > 2.17.1 > >
On 1/4/19 3:28 PM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Add MicroBlaze CPU properties to enable exceptions on failed > bus accesses. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> > --- > target/microblaze/cpu.c | 12 +++++++++++- > target/microblaze/cpu.h | 2 ++ > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c > index 49876b19b3..5596cd5485 100644 > --- a/target/microblaze/cpu.c > +++ b/target/microblaze/cpu.c > @@ -202,7 +202,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | > (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | > (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | > - (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); > + (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | > + (cpu->cfg.dopb_bus_exception ? > + PVR2_DOPB_BUS_EXC_MASK : 0) | > + (cpu->cfg.iopb_bus_exception ? > + PVR2_IOPB_BUS_EXC_MASK : 0); > > env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? > PVR5_DCACHE_WRITEBACK_MASK : 0; > @@ -265,6 +269,12 @@ static Property mb_properties[] = { > DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, > false), > DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), > + /* Enables bus exceptions on failed data accesses (load/stores). */ > + DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU, > + cfg.dopb_bus_exception, false), > + /* Enables bus exceptions on failed instruction fetches. */ > + DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, > + cfg.iopb_bus_exception, false), > DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), > DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), > DEFINE_PROP_END_OF_LIST(), > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index 03ca91007d..792bbc97c7 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -308,6 +308,8 @@ struct MicroBlazeCPU { > bool use_mmu; > bool dcache_writeback; > bool endi; > + bool dopb_bus_exception; > + bool iopb_bus_exception; > char *version; > uint8_t pvr; > } cfg; >
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 49876b19b3..5596cd5485 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -202,7 +202,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | - (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); + (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | + (cpu->cfg.dopb_bus_exception ? + PVR2_DOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.iopb_bus_exception ? + PVR2_IOPB_BUS_EXC_MASK : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -265,6 +269,12 @@ static Property mb_properties[] = { DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), + /* Enables bus exceptions on failed data accesses (load/stores). */ + DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU, + cfg.dopb_bus_exception, false), + /* Enables bus exceptions on failed instruction fetches. */ + DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, + cfg.iopb_bus_exception, false), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), DEFINE_PROP_END_OF_LIST(), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 03ca91007d..792bbc97c7 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -308,6 +308,8 @@ struct MicroBlazeCPU { bool use_mmu; bool dcache_writeback; bool endi; + bool dopb_bus_exception; + bool iopb_bus_exception; char *version; uint8_t pvr; } cfg;