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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v7 29/35] target/riscv: Remove gen_system() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Peer Adelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Bastian Koppelmann with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3d49c8ed4054..65bedc966497 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -474,33 +474,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) tcg_temp_free_i32(t0); } -static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1, - int csr) -{ - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - - switch (opc) { - case OPC_RISC_ECALL: - switch (csr) { - case 0x0: /* ECALL */ - /* always generates U-level ECALL, fixed in do_interrupt handler */ - generate_exception(ctx, RISCV_EXCP_U_ECALL); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - break; - case 0x1: /* EBREAK */ - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - break; - default: - gen_exception_illegal(ctx); - break; - } - break; - } -} - static void decode_RV32_64C0(DisasContext *ctx) { uint8_t funct3 = extract32(ctx->opcode, 13, 3); @@ -675,7 +648,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn); static void decode_RV32_64G(DisasContext *ctx) { - int rs1, rd; uint32_t op; /* We do not do misaligned address check here: the address should never be @@ -684,14 +656,8 @@ static void decode_RV32_64G(DisasContext *ctx) * perform the misaligned instruction fetch */ op = MASK_OP_MAJOR(ctx->opcode); - rs1 = GET_RS1(ctx->opcode); - rd = GET_RD(ctx->opcode); switch (op) { - case OPC_RISC_SYSTEM: - gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, - (ctx->opcode & 0xFFF00000) >> 20); - break; default: gen_exception_illegal(ctx); break;