diff mbox series

[PULL,11/34] riscv: virt: Correct pci "bus-range" encoding

Message ID	20190628173227.31925-12-palmer@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> Date: Fri, 28 Jun 2019 10:32:04 -0700 Message-Id: <20190628173227.31925-12-palmer@sifive.com> In-Reply-To: <20190628173227.31925-1-palmer@sifive.com> References: <20190628173227.31925-1-palmer@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding Precedence: list Cc: Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt <palmer@sifive.com> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	[PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props \| expand [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props [PULL,02/34] sifive_prci: Read and write PRCI registers [PULL,03/34] target/riscv: Fix PMP range boundary address bug [PULL,04/34] target/riscv: Implement riscv_cpu_unassigned_access [PULL,05/34] RISC-V: Only Check PMP if MMU translation succeeds [PULL,06/34] RISC-V: Raise access fault exceptions on PMP violations [PULL,07/34] RISC-V: Check for the effective memory privilege mode during PMP checks [PULL,08/34] RISC-V: Check PMP during Page Table Walks [PULL,09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off [PULL,10/34] RISC-V: Fix a PMP check with the correct access size [PULL,11/34] riscv: virt: Correct pci "bus-range" encoding [PULL,12/34] RISC-V: Fix a memory leak when realizing a sifive_e [PULL,13/34] target/riscv: Restructure deprecatd CPUs [PULL,14/34] target/riscv: Add the privledge spec version 1.11.0 [PULL,15/34] target/riscv: Add the mcountinhibit CSR [PULL,16/34] target/riscv: Set privledge spec 1.11.0 as default [PULL,17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 [PULL,18/34] target/riscv: Require either I or E base extension [PULL,19/34] target/riscv: Remove user version information [PULL,20/34] target/riscv: Add support for disabling/enabling Counters [PULL,21/34] RISC-V: Add support for the Zifencei extension [PULL,22/34] RISC-V: Add support for the Zicsr extension [PULL,23/34] RISC-V: Clear load reservations on context switch and SC [PULL,24/34] RISC-V: Update syscall list for 32-bit support. [PULL,25/34] riscv: virt: Add cpu-topology DT node. [PULL,26/34] disas/riscv: Disassemble reserved compressed encodings as illegal [PULL,27/34] disas/riscv: Fix `rdinstreth` constraint [PULL,28/34] riscv: sifive_u: Do not create hard-coded phandles in DT [PULL,29/34] riscv: sifive_u: Update the plic hart config to support multicore [PULL,30/34] hw/riscv: Split out the boot functions [PULL,31/34] hw/riscv: Add support for loading a firmware [PULL,32/34] hw/riscv: Extend the kernel loading support [PULL,33/34] roms: Add OpenSBI version 0.3 [PULL,34/34] hw/riscv: Load OpenSBI as the default firmware

Commit Message

Palmer Dabbelt June 28, 2019, 5:32 p.m. UTC

From: Bin Meng <bmeng.cn@gmail.com>

The largest pci bus number should be calculated from ECAM size,
instead of its base address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 84d94d0c42d8..487f61404b21 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -298,7 +298,7 @@  static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
     qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
     qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
-                           memmap[VIRT_PCIE_ECAM].base /
+                           memmap[VIRT_PCIE_ECAM].size /
                                PCIE_MMCFG_SIZE_MIN - 1);
     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
     qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,