| Message ID | 20190703084048.6980-1-palmer@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 | expand |
On Wed, 3 Jul 2019 at 09:41, Palmer Dabbelt <palmer@sifive.com> wrote: > > merged tag 'mips-queue-jun-21-2019' > The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: > > Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 15:40:50 +0100) > > are available in the Git repository at: > > git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1-v3 > > for you to fetch changes up to 395fd69582a00b76a89c12d9c074055a9d207997: > > hw/riscv: Extend the kernel loading support (2019-06-27 02:47:06 -0700) > > ---------------------------------------------------------------- > RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 > > This pull request contains a handful of patches that I'd like to target > for the 4.1 soft freeze. There are a handful of new features: > > * Support for the 1.11.0, the latest privileged specification. > * Support for reading and writing the PRCI registers. > * Better control over the ISA of the target machine. > * Support for the cpu-topology device tree node. > > Additionally, there are a handful of bug fixes including: > > * Load reservations are now broken by both store conditional and by > scheduling, which fixes issues with parallel applications. > * Various fixes to the PMP implementation. > * Fixes to the 32-bit linux-user syscall ABI. > * Various fixes for instruction decodeing. > * A fix to the PCI device tree "bus-range" property. > > This boots 32-bit and 64-bit OpenEmbedded. > > Changes since v2 [riscv-for-master-4.1-sf1-v2]: > > * Dropped OpenSBI. > > Changes since v1 [riscv-for-master-4.1-sf1]: > > * Contains a fix to the sifive_u OpenSBI integration. Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1 for any user-visible changes. -- PMM
merged tag 'mips-queue-jun-21-2019' The following changes since commit 474f3938d79ab36b9231c9ad3b5a9314c2aeacde: Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' into staging (2019-06-21 15:40:50 +0100) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1-v3 for you to fetch changes up to 395fd69582a00b76a89c12d9c074055a9d207997: hw/riscv: Extend the kernel loading support (2019-06-27 02:47:06 -0700) ---------------------------------------------------------------- RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 This pull request contains a handful of patches that I'd like to target for the 4.1 soft freeze. There are a handful of new features: * Support for the 1.11.0, the latest privileged specification. * Support for reading and writing the PRCI registers. * Better control over the ISA of the target machine. * Support for the cpu-topology device tree node. Additionally, there are a handful of bug fixes including: * Load reservations are now broken by both store conditional and by scheduling, which fixes issues with parallel applications. * Various fixes to the PMP implementation. * Fixes to the 32-bit linux-user syscall ABI. * Various fixes for instruction decodeing. * A fix to the PCI device tree "bus-range" property. This boots 32-bit and 64-bit OpenEmbedded. Changes since v2 [riscv-for-master-4.1-sf1-v2]: * Dropped OpenSBI. Changes since v1 [riscv-for-master-4.1-sf1]: * Contains a fix to the sifive_u OpenSBI integration. ---------------------------------------------------------------- Alistair Francis (12): target/riscv: Allow setting ISA extensions via CPU props target/riscv: Restructure deprecatd CPUs target/riscv: Add the privledge spec version 1.11.0 target/riscv: Add the mcountinhibit CSR target/riscv: Set privledge spec 1.11.0 as default qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 target/riscv: Require either I or E base extension target/riscv: Remove user version information target/riscv: Add support for disabling/enabling Counters hw/riscv: Split out the boot functions hw/riscv: Add support for loading a firmware hw/riscv: Extend the kernel loading support Atish Patra (1): riscv: virt: Add cpu-topology DT node. Bin Meng (3): riscv: virt: Correct pci "bus-range" encoding riscv: sifive_u: Do not create hard-coded phandles in DT riscv: sifive_u: Update the plic hart config to support multicore Dayeol Lee (1): target/riscv: Fix PMP range boundary address bug Hesham Almatary (6): RISC-V: Only Check PMP if MMU translation succeeds RISC-V: Raise access fault exceptions on PMP violations RISC-V: Check for the effective memory privilege mode during PMP checks RISC-V: Check PMP during Page Table Walks RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off RISC-V: Fix a PMP check with the correct access size Jim Wilson (1): RISC-V: Update syscall list for 32-bit support. Joel Sing (1): RISC-V: Clear load reservations on context switch and SC Michael Clark (2): target/riscv: Implement riscv_cpu_unassigned_access disas/riscv: Disassemble reserved compressed encodings as illegal Nathaniel Graff (1): sifive_prci: Read and write PRCI registers Palmer Dabbelt (3): RISC-V: Fix a memory leak when realizing a sifive_e RISC-V: Add support for the Zifencei extension RISC-V: Add support for the Zicsr extension Wladimir J. van der Laan (1): disas/riscv: Fix `rdinstreth` constraint disas/riscv.c | 65 ++++++++---- hw/riscv/Makefile.objs | 1 + hw/riscv/boot.c | 105 +++++++++++++++++++ hw/riscv/sifive_e.c | 30 ++---- hw/riscv/sifive_prci.c | 49 +++++++-- hw/riscv/sifive_u.c | 54 +++++----- hw/riscv/spike.c | 21 +--- hw/riscv/virt.c | 79 ++++++-------- include/hw/riscv/boot.h | 29 ++++++ include/hw/riscv/sifive_e.h | 2 + include/hw/riscv/sifive_prci.h | 32 ++++++ linux-user/riscv/syscall_nr.h | 15 ++- qemu-deprecated.texi | 8 ++ target/riscv/cpu.c | 137 ++++++++++++++++++------- target/riscv/cpu.h | 33 ++++-- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 55 +++++++++- target/riscv/csr.c | 30 +++++- target/riscv/insn_trans/trans_privileged.inc.c | 2 +- target/riscv/insn_trans/trans_rva.inc.c | 8 +- target/riscv/insn_trans/trans_rvi.inc.c | 4 + target/riscv/pmp.c | 17 +-- target/riscv/pmp.h | 2 +- target/riscv/translate.c | 3 + 24 files changed, 583 insertions(+), 199 deletions(-) create mode 100644 hw/riscv/boot.c create mode 100644 include/hw/riscv/boot.h From Palmer Dabbelt <palmer@sifive.com> # This line is ignored. From: Palmer Dabbelt <palmer@sifive.com> Reply-To: Subject: In-Reply-To: