diff mbox series

[PULL,32/32] hw/riscv: Extend the kernel loading support

Message ID	20190703084048.6980-33-palmer@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> Date: Wed, 3 Jul 2019 01:40:48 -0700 Message-Id: <20190703084048.6980-33-palmer@sifive.com> In-Reply-To: <20190703084048.6980-1-palmer@sifive.com> References: <20190703084048.6980-1-palmer@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 32/32] hw/riscv: Extend the kernel loading support Precedence: list Cc: Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt <palmer@sifive.com> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 \| expand [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 [PULL,02/32] sifive_prci: Read and write PRCI registers [PULL,03/32] target/riscv: Fix PMP range boundary address bug [PULL,04/32] target/riscv: Implement riscv_cpu_unassigned_access [PULL,05/32] RISC-V: Only Check PMP if MMU translation succeeds [PULL,06/32] RISC-V: Raise access fault exceptions on PMP violations [PULL,07/32] RISC-V: Check for the effective memory privilege mode during PMP checks [PULL,08/32] RISC-V: Check PMP during Page Table Walks [PULL,09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off [PULL,10/32] RISC-V: Fix a PMP check with the correct access size [PULL,11/32] riscv: virt: Correct pci "bus-range" encoding [PULL,12/32] RISC-V: Fix a memory leak when realizing a sifive_e [PULL,13/32] target/riscv: Restructure deprecatd CPUs [PULL,14/32] target/riscv: Add the privledge spec version 1.11.0 [PULL,15/32] target/riscv: Add the mcountinhibit CSR [PULL,16/32] target/riscv: Set privledge spec 1.11.0 as default [PULL,17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 [PULL,18/32] target/riscv: Require either I or E base extension [PULL,19/32] target/riscv: Remove user version information [PULL,20/32] target/riscv: Add support for disabling/enabling Counters [PULL,21/32] RISC-V: Add support for the Zifencei extension [PULL,22/32] RISC-V: Add support for the Zicsr extension [PULL,23/32] RISC-V: Clear load reservations on context switch and SC [PULL,24/32] RISC-V: Update syscall list for 32-bit support. [PULL,25/32] riscv: virt: Add cpu-topology DT node. [PULL,26/32] disas/riscv: Disassemble reserved compressed encodings as illegal [PULL,27/32] disas/riscv: Fix `rdinstreth` constraint [PULL,28/32] riscv: sifive_u: Do not create hard-coded phandles in DT [PULL,29/32] riscv: sifive_u: Update the plic hart config to support multicore [PULL,30/32] hw/riscv: Split out the boot functions [PULL,31/32] hw/riscv: Add support for loading a firmware [PULL,32/32] hw/riscv: Extend the kernel loading support

Commit Message

Palmer Dabbelt July 3, 2019, 8:40 a.m. UTC

From: Alistair Francis <alistair.francis@wdc.com>

Extend the RISC-V kernel loader to support Image and uImage files.
A Linux kernel can now be booted with:

    qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel Image

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/boot.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff mbox series

Patch

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 883df49a0c65..ff023f42d01d 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -56,12 +56,22 @@  target_ulong riscv_load_kernel(const char *kernel_filename)
     uint64_t kernel_entry, kernel_high;
 
     if (load_elf(kernel_filename, NULL, NULL, NULL,
-                 &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) < 0) {
-        error_report("could not load kernel '%s'", kernel_filename);
-        exit(1);
+                 &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) > 0) {
+        return kernel_entry;
     }
 
-    return kernel_entry;
+    if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
+                       NULL, NULL, NULL) > 0) {
+        return kernel_entry;
+    }
+
+    if (load_image_targphys_as(kernel_filename, KERNEL_BOOT_ADDRESS,
+                               ram_size, NULL) > 0) {
+        return KERNEL_BOOT_ADDRESS;
+    }
+
+    error_report("could not load kernel '%s'", kernel_filename);
+    exit(1);
 }
 
 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,