@@ -777,6 +777,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
#define TCG_SGX_12_0_EAX_FEATURES 0
#define TCG_SGX_12_1_EAX_FEATURES 0
+#define TCG_SGX_12_1_EBX_FEATURES 0
typedef enum FeatureWordType {
CPUID_FEATURE_WORD,
@@ -1264,6 +1265,25 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = TCG_SGX_12_1_EAX_FEATURES,
},
+ [FEAT_SGX_12_1_EBX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "sgx-exinfo" , NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0x12,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EBX,
+ },
+ .tcg_features = TCG_SGX_12_1_EBX_FEATURES,
+ },
};
typedef struct X86RegisterInfo32 {
@@ -508,6 +508,7 @@ typedef enum FeatureWord {
FEAT_CORE_CAPABILITY,
FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
+ FEAT_SGX_12_1_EBX, /* CPUID[EAX=0x12,ECX=1].EBX (SGX MISCSELECT[31:0]) */
FEATURE_WORDS,
} FeatureWord;
CPUID leaf 12_1_EBX is an Intel-defined feature bits leaf enumerating the platform's SGX extended capabilities. Currently there is a single capabilitiy: - EXINFO: record information about #PFs and #GPs in the enclave's SSA Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> --- target/i386/cpu.c | 20 ++++++++++++++++++++ target/i386/cpu.h | 1 + 2 files changed, 21 insertions(+)