From patchwork Tue Sep 10 19:04:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11140623 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3DC72912 for ; Wed, 11 Sep 2019 08:38:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1E04720863 for ; Wed, 11 Sep 2019 08:38:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1E04720863 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:47970 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7y8W-00055f-Mk for patchwork-qemu-devel@patchwork.kernel.org; Wed, 11 Sep 2019 04:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57158) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7xvr-0007bp-T8 for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:24:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7xvq-0006UR-Pn for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:24:55 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:55140) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7xvq-0006U4-Jt for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:24:54 -0400 Received: by mail-wm1-f66.google.com with SMTP id p7so2327074wmp.4 for ; Wed, 11 Sep 2019 01:24:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=3hJQGoN/dkKnxfz2wZzkBe8IK9Gek4+jV7PzGIOzZB8=; b=B9kSOAPoPI/6z6HnRPOZdNJ7MCo8fBD4xbCjMCg+mn4MoAE6h6vflj4i2RXQn5y+OV /5As0I72YJ9z+c6Gkbzr9bhNjCiNt/rAUNmVlX1cKSg1cVqvVxHIyQ7tGzByX2/rCbzG 9XkhUrpsTnF2T9zUfec5OM5ynF2G+pktey+1urxdw2aBySfiKH0aoKoYNMXz7uQCk+4C Bq2NH5Mz3s9558qbMoSriqo2qjU3MHPlBG+Euu64qmSPbhuu+86P9VUXC1kSaomr+8LW DdRhyXFF27V9GWrPnpQ0lHFx/fA8JuGzmIo8H4IwzSkgOa977kVcveLQIalRlTQWh+TP QbAg== X-Gm-Message-State: APjAAAU2LtsLySz/bz1r5gzy5QQjlozQPOHaKfaL7fWlNvqE/W1eW91V tsOOFklPiJEslUk28onK4ORZYQ== X-Google-Smtp-Source: APXvYqy4OOqHjWu2bFFeY9E1qUXYpCK7loKq9UIfr+RugRSB4B5heRLAh7wJY48pHiTOkjy7vcJXcQ== X-Received: by 2002:a7b:cf11:: with SMTP id l17mr2799594wmg.162.1568190293264; Wed, 11 Sep 2019 01:24:53 -0700 (PDT) Received: from localhost ([148.69.85.38]) by smtp.gmail.com with ESMTPSA id s12sm29134876wra.82.2019.09.11.01.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2019 01:24:52 -0700 (PDT) Date: Tue, 10 Sep 2019 12:04:39 -0700 Message-Id: <20190910190513.21160-14-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190910190513.21160-1-palmer@sifive.com> References: <20190910190513.21160-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.66 Subject: [Qemu-devel] [PULL 13/47] riscv: sifive_test: Add reset functionality X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This adds a reset opcode for sifive_test device to trigger a system reset for testing purpose. Signed-off-by: Bin Meng Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_test.c | 4 ++++ include/hw/riscv/sifive_test.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c index afbb3aaf34..3557e16701 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/riscv/sifive_test.c @@ -22,6 +22,7 @@ #include "hw/hw.h" #include "hw/sysbus.h" #include "qemu/module.h" +#include "sysemu/runstate.h" #include "target/riscv/cpu.h" #include "hw/hw.h" #include "hw/riscv/sifive_test.h" @@ -42,6 +43,9 @@ static void sifive_test_write(void *opaque, hwaddr addr, exit(code); case FINISHER_PASS: exit(0); + case FINISHER_RESET: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; default: break; } diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h index 3a603a6ead..1ec416ac1b 100644 --- a/include/hw/riscv/sifive_test.h +++ b/include/hw/riscv/sifive_test.h @@ -36,7 +36,8 @@ typedef struct SiFiveTestState { enum { FINISHER_FAIL = 0x3333, - FINISHER_PASS = 0x5555 + FINISHER_PASS = 0x5555, + FINISHER_RESET = 0x7777 }; DeviceState *sifive_test_create(hwaddr addr);