[PULL,21/47] riscv: roms: Remove executable attribute of opensbi images

From: Bin Meng <bmeng.cn@gmail.com>

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Date: Tue, 10 Sep 2019 12:04:47 -0700
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From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Subject: [Qemu-devel] [PULL 21/47] riscv: roms: Remove executable attribute
 of opensbi images
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Cc: Alistair Francis <alistair.francis@wdc.com>,
 Bin Meng <bmeng.cn@gmail.com>,
 qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
 Palmer Dabbelt <palmer@sifive.com>
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Message ID	20190910190513.21160-22-palmer@sifive.com (mailing list archive)
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Headers	show Return-Path: <SRS0=B9BE=XG=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 38F7420863 Date: Tue, 10 Sep 2019 12:04:47 -0700 Message-Id: <20190910190513.21160-22-palmer@sifive.com> In-Reply-To: <20190910190513.21160-1-palmer@sifive.com> References: <20190910190513.21160-1-palmer@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt <palmer@sifive.com> To: Peter Maydell <peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images Precedence: list Cc: Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt <palmer@sifive.com> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 \| expand [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 [PULL,02/47] riscv: sivive_u: Add dummy serial clock and aliases entry for uart [PULL,03/47] riscv: sifive_u: Fix clock-names property for ethernet node [PULL,04/47] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation [PULL,05/47] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events [PULL,06/47] riscv: plic: Remove unused interrupt functions [PULL,07/47] target/riscv: Create function to test if FP is enabled [PULL,08/47] target/riscv: Update the Hypervisor CSRs to v0.4 [PULL,09/47] riscv: rv32: Root page table address can be larger than 32-bit [PULL,10/47] riscv: Add a helper routine for finding firmware [PULL,11/47] riscv: Resolve full path of the given bios image [PULL,12/47] riscv: hmp: Add a command to show virtual memory mappings [PULL,13/47] riscv: sifive_test: Add reset functionality [PULL,14/47] riscv: hw: Remove duplicated "hw/hw.h" inclusion [PULL,15/47] riscv: hw: Remove superfluous "linux, phandle" property [PULL,16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [PULL,17/47] riscv: hw: Remove not needed PLIC properties in device tree [PULL,18/47] riscv: hw: Change create_fdt() to return void [PULL,19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead [PULL,20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h [PULL,21/47] riscv: roms: Remove executable attribute of opensbi images [PULL,22/47] riscv: sifive_u: Remove the unnecessary include of prci header [PULL,23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [PULL,24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [PULL,25/47] riscv: sifive_e: prci: Update the PRCI register block size [PULL,26/47] riscv: sifive_e: Drop sifive_mmio_emulate() [PULL,27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [PULL,28/47] riscv: hart: Extract hart realize to a separate routine [PULL,29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array [PULL,30/47] riscv: sifive_u: Set the minimum number of cpus to 2 [PULL,31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [PULL,32/47] riscv: sifive_u: Update PLIC hart topology configuration string [PULL,33/47] riscv: sifive: Implement PRCI model for FU540 [PULL,34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes [PULL,35/47] riscv: sifive_u: Add PRCI block to the SoC [PULL,36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [PULL,37/47] riscv: sifive_u: Update UART base addresses and IRQs [PULL,38/47] riscv: sifive_u: Change UART node name in device tree [PULL,39/47] riscv: roms: Update default bios for sifive_u machine [PULL,40/47] riscv: sifive: Implement a model for SiFive FU540 OTP [PULL,41/47] riscv: sifive_u: Instantiate OTP memory with a serial number [PULL,42/47] riscv: sifive_u: Fix broken GEM support [PULL,43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [PULL,44/47] riscv: sifive_u: Update model and compatible strings in device tree [PULL,45/47] target/riscv: Use both register name and ABI name [PULL,46/47] target/riscv: Fix mstatus dirty mask [PULL,47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point

[PULL,21/47] riscv: roms: Remove executable attribute of opensbi images

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