From patchwork Tue Sep 10 19:04:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11140655 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03FBC112B for ; Wed, 11 Sep 2019 08:48:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CD47921D79 for ; Wed, 11 Sep 2019 08:48:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CD47921D79 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:48074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7yIb-0007oJ-Iw for patchwork-qemu-devel@patchwork.kernel.org; Wed, 11 Sep 2019 04:48:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57472) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7xw9-00082f-LO for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7xw8-0006hv-8T for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:13 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:33216) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7xw8-0006h3-1a for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:12 -0400 Received: by mail-wr1-f66.google.com with SMTP id u16so23489064wrr.0 for ; Wed, 11 Sep 2019 01:25:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=1Aa/dt536fZQJDPGXIgu6PlloiU8ircw4pByaQneOdE=; b=NeMmGvOrq7XHtoU5wMxoEsLkKZJqoP7OPBE3Pe9GxXesqtuI2VctVXVx6r3uooZ+ak FBO6LEZU6v3wnIrNhhJ5hR+y96KLjkdOCTZC8zd6jXGp/jY8bH0pJzbevDqj0yUx3ABx lTi9upo4ji079UVFJPAX53jw5MWhSmRoM9+NCGHTUn17UcW3DoNCPvSjgNZXTWUHDkLS 69kKohxRFkSbM2qjbFFzyWSKQgncrofYrMGclPeqULk4z6c1skTL8BJ6DcSii/qeYTpp C2IVEKQ1fQ0x4xNhlvAV7GMONqn0wKD1NjIHT6lCnThXDMm7bzD9yr+OCYeGFDkAC8Q3 4DQQ== X-Gm-Message-State: APjAAAV59H2nc2W3YlF+z3R8QkBIPBJ8CMRexD9aRIhUjKQ0DzcqrJel BXEqd7LJlf02xyeWwmFmSWwOzA== X-Google-Smtp-Source: APXvYqztvuGftlNGNlTvlJY5JDe7/ufFSrd7n7So0VEuF1Bqw2NyFihOf9drfTk7FcJQ4KkVGruAhA== X-Received: by 2002:a5d:428c:: with SMTP id k12mr17162wrq.196.1568190310763; Wed, 11 Sep 2019 01:25:10 -0700 (PDT) Received: from localhost ([148.69.85.38]) by smtp.gmail.com with ESMTPSA id e20sm2256957wme.3.2019.09.11.01.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2019 01:25:10 -0700 (PDT) Date: Tue, 10 Sep 2019 12:04:52 -0700 Message-Id: <20190910190513.21160-27-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190910190513.21160-1-palmer@sifive.com> References: <20190910190513.21160-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.66 Subject: [Qemu-devel] [PULL 26/47] riscv: sifive_e: Drop sifive_mmio_emulate() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Use create_unimplemented_device() instead. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/Kconfig | 1 + hw/riscv/sifive_e.c | 23 ++++++++--------------- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 8674211085..33e54b031d 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -12,6 +12,7 @@ config SIFIVE_E bool select HART select SIFIVE + select UNIMP config SIFIVE_U bool diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1428a99fce..0f9d641a0e 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -36,6 +36,7 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/char/serial.h" +#include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" @@ -74,14 +75,6 @@ static const struct MemmapEntry { [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } }; -static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, - uintptr_t offset, uintptr_t length) -{ - MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); - memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); - memory_region_add_subregion(parent, offset, mock_mmio); -} - static void riscv_sifive_e_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_e_memmap; @@ -172,7 +165,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) sifive_clint_create(memmap[SIFIVE_E_CLINT].base, memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", + create_unimplemented_device("riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); @@ -199,19 +192,19 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", + create_unimplemented_device("riscv.sifive.e.qspi0", memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", + create_unimplemented_device("riscv.sifive.e.pwm0", memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", + create_unimplemented_device("riscv.sifive.e.qspi1", memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", + create_unimplemented_device("riscv.sifive.e.pwm1", memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2", + create_unimplemented_device("riscv.sifive.e.qspi2", memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2", + create_unimplemented_device("riscv.sifive.e.pwm2", memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); /* Flash memory */