From patchwork Tue Sep 10 19:04:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11140677 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E9617112B for ; Wed, 11 Sep 2019 08:55:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CA63E21A4C for ; Wed, 11 Sep 2019 08:55:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CA63E21A4C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:48148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7yP2-0007eh-In for patchwork-qemu-devel@patchwork.kernel.org; Wed, 11 Sep 2019 04:55:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57534) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7xwC-00086l-Nl for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7xwB-0006kP-3U for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:16 -0400 Received: from mail-wr1-f48.google.com ([209.85.221.48]:39220) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7xwA-0006jp-S1 for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:15 -0400 Received: by mail-wr1-f48.google.com with SMTP id t16so23452252wra.6 for ; Wed, 11 Sep 2019 01:25:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=dn6ffCPkA7oUVq7UkAAzaviL3Pr9DX2pgFSlHwRglF4=; b=gEEOaNjpTiZg1Ph8/m7VSAmt9HXJAtTikWooQ9M8H0oz3l59PElOw47kbSShUJKx74 X9aqyMSx6F9uGdaEWwvvW+Fjvm0SGj0YPoNGq0JGv4lsvtYEJyQrg3Hbq2sW3F6B5i20 /BTo2nZpL02Anqnu9faj7AKijAUkK7Tk/QOGgp53CFN1lmmmhCtlryCPKx5oZdwrwCzr uYMXDJrVwB3g2Mmm/wQ6k1dcvAGcOX+XgbdtoqR4qJSWq35aftJVPY/JoXNrWjy+HyMN Nv7Qzy8obGbcYLL4qegZSSNE4VnP8ciMSpXF599TQ1njKfZn0DWy48cpcuSMfGm1ky93 MO/A== X-Gm-Message-State: APjAAAU4vptbo5JnOjN3jJbQa2qAB2fZpTQZbiGDiS2UsbX8khwZc33n y7rEyhyhQHJATESOkZExow6a6Q== X-Google-Smtp-Source: APXvYqyu7FNS4ohUvfOzQsK9YSsqNC4rpJVPLnqNuOK4DBNxfuXZZx57LtY544X2FHhXarnU9MvvCg== X-Received: by 2002:adf:b652:: with SMTP id i18mr17845wre.126.1568190313477; Wed, 11 Sep 2019 01:25:13 -0700 (PDT) Received: from localhost ([148.69.85.38]) by smtp.gmail.com with ESMTPSA id v2sm4149372wmf.18.2019.09.11.01.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2019 01:25:13 -0700 (PDT) Date: Tue, 10 Sep 2019 12:04:54 -0700 Message-Id: <20190910190513.21160-29-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190910190513.21160-1-palmer@sifive.com> References: <20190910190513.21160-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.48 Subject: [Qemu-devel] [PULL 28/47] riscv: hart: Extract hart realize to a separate routine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create homogeneous harts. Exact the hart realize to a separate routine in preparation for supporting multiple hart arrays. Note the file header says the RISC-V hart array holds the state of a heterogeneous array of RISC-V harts, which is not true. Update the comment to mention homogeneous array of RISC-V harts. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/riscv_hart.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index d0f3199968..6620e41cb7 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -3,7 +3,7 @@ * * Copyright (c) 2017 SiFive, Inc. * - * Holds the state of a heterogenous array of RISC-V harts + * Holds the state of a homogeneous array of RISC-V harts * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -39,26 +39,33 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } +static void riscv_hart_realize(RISCVHartArrayState *s, int idx, + char *cpu_type, Error **errp) +{ + Error *err = NULL; + + object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], + sizeof(RISCVCPU), cpu_type, + &error_abort, NULL); + s->harts[idx].env.mhartid = idx; + qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); + object_property_set_bool(OBJECT(&s->harts[idx]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } +} + static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); - Error *err = NULL; int n; s->harts = g_new0(RISCVCPU, s->num_harts); for (n = 0; n < s->num_harts; n++) { - object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n], - sizeof(RISCVCPU), s->cpu_type, - &error_abort, NULL); - s->harts[n].env.mhartid = n; - qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]); - object_property_set_bool(OBJECT(&s->harts[n]), true, - "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } + riscv_hart_realize(s, n, s->cpu_type, errp); } }