From patchwork Tue Sep 10 19:05:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 11140671 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8043112B for ; Wed, 11 Sep 2019 08:52:17 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C814B21A4C for ; Wed, 11 Sep 2019 08:52:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C814B21A4C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:48110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7yMK-0004LX-Aw for patchwork-qemu-devel@patchwork.kernel.org; Wed, 11 Sep 2019 04:52:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57749) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i7xwN-0008P0-4e for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i7xwL-0006r4-PX for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:26 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:52243) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i7xwL-0006qq-JB for qemu-devel@nongnu.org; Wed, 11 Sep 2019 04:25:25 -0400 Received: by mail-wm1-f67.google.com with SMTP id t17so2328545wmi.2 for ; Wed, 11 Sep 2019 01:25:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=zKS0Ptw6RqKS92hxW8V/YLR4EXZgqfiBzy8ZWgOdiHs=; b=bnKk1FB1HJbZxPD2/HsVruibBcFofrxoBHmozZJJRRidliavvvcDGi+MLqYJ1fuMTC wqxC57I7Yt7lgr3fjva1BSO047KCgm1MXu3JNFMnPeZ8MeJhyj437jjVi7vLeT/theMR icvLdM65DKQ5sUNcZ6uB8+kG48x3y1O7LKBuVmWq21FfFI9QIrcBu4gdovVXCDs5nSc3 kxdKPWV66HzsReKeBZxcQZBcW63deQmZ/fWvhtILpPvc8dGPSKDhkAbVg7jmhSaPa805 JrQ1c646Wj6v+Yw08XbOJGUEiiZW3GH54zywoXS6clSd4zWRV4OKadeAA+5RgB1O+b9d XZ4Q== X-Gm-Message-State: APjAAAWwqvskj1aL3PGr0N1VGt4prtMXDFqruw11zio8N6ZQ/Hvtn4zn PhemTNpz8h50SW6owaI7Gw6KLA== X-Google-Smtp-Source: APXvYqz1v/nztKnreMNb2jwoHVEdZoOFBccPo2VCZShzDyOTR4o4C6kz9lIf2gy0t/SPhBzfj7alCA== X-Received: by 2002:a1c:cbcc:: with SMTP id b195mr3115867wmg.80.1568190324356; Wed, 11 Sep 2019 01:25:24 -0700 (PDT) Received: from localhost ([148.69.85.38]) by smtp.gmail.com with ESMTPSA id y186sm3504573wmd.26.2019.09.11.01.25.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2019 01:25:23 -0700 (PDT) Date: Tue, 10 Sep 2019 12:05:02 -0700 Message-Id: <20190910190513.21160-37-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190910190513.21160-1-palmer@sifive.com> References: <20190910190513.21160-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.67 Subject: [Qemu-devel] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 7 ++++--- include/hw/riscv/sifive_u_prci.h | 10 ++++++++++ 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ff2e28e26c..ea21095513 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -78,7 +78,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, int cpu; uint32_t *cells; char *nodename; - char ethclk_names[] = "pclk\0hclk\0tx_clk"; + char ethclk_names[] = "pclk\0hclk"; uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; uint32_t uartclk_phandle; uint32_t hfclk_phandle, rtcclk_phandle; @@ -263,7 +263,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", - ethclk_phandle, ethclk_phandle, ethclk_phandle); + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, sizeof(ethclk_names)); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); @@ -293,7 +293,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); - qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h index 60a2eab0e9..0a531fdadc 100644 --- a/include/hw/riscv/sifive_u_prci.h +++ b/include/hw/riscv/sifive_u_prci.h @@ -78,4 +78,14 @@ typedef struct SiFiveUPRCIState { uint32_t clkmuxstatus; } SiFiveUPRCIState; +/* + * Clock indexes for use by Device Tree data and the PRCI driver. + * + * These values are from sifive-fu540-prci.h in the Linux kernel. + */ +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + #endif /* HW_SIFIVE_U_PRCI_H */