Message ID | 20191115044104.4197-2-palmer@dabbelt.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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[67.161.15.180]) by smtp.gmail.com with ESMTPSA id a12sm9419246pfk.188.2019.11.14.20.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 20:41:26 -0800 (PST) Subject: [PULL 1/4] remove unnecessary ifdef TARGET_RISCV64 Date: Thu, 14 Nov 2019 20:41:01 -0800 Message-Id: <20191115044104.4197-2-palmer@dabbelt.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191115044104.4197-1-palmer@dabbelt.com> References: <20191115044104.4197-1-palmer@dabbelt.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt <palmer@dabbelt.com> To: Peter Maydell <peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: Palmer Dabbelt <palmer@sifive.com>, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, "hiroyuki.obinata" <hiroyuki.obinata@gmail.com> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> |
Series |
[PULL,1/4] remove unnecessary ifdef TARGET_RISCV64
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expand
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diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b26533d4fd78..ab6a891dc381 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,12 +64,10 @@ static const int tcg_memop_lookup[8] = { [0] = MO_SB, [1] = MO_TESW, [2] = MO_TESL, + [3] = MO_TEQ, [4] = MO_UB, [5] = MO_TEUW, -#ifdef TARGET_RISCV64 - [3] = MO_TEQ, [6] = MO_TEUL, -#endif }; #endif