@@ -100,7 +100,7 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
case S390_CPU_RESET_INITIAL:
/* initial reset does not clear everything! */
memset(&env->start_initial_reset_fields, 0,
- offsetof(CPUS390XState, end_reset_fields) -
+ offsetof(CPUS390XState, start_normal_reset_fields) -
offsetof(CPUS390XState, start_initial_reset_fields));
/* architectured initial value for Breaking-Event-Address register */
@@ -123,6 +123,11 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
&env->fpu_status);
/* fall through */
case S390_CPU_RESET_NORMAL:
+ env->psw.mask &= ~PSW_MASK_RI;
+ memset(&env->start_normal_reset_fields, 0,
+ offsetof(CPUS390XState, end_reset_fields) -
+ offsetof(CPUS390XState, start_normal_reset_fields));
+
env->pfault_token = -1UL;
env->bpbc = false;
break;
@@ -58,7 +58,6 @@ struct CPUS390XState {
*/
uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */
uint32_t aregs[16]; /* access registers */
- uint8_t riccb[64]; /* runtime instrumentation control */
uint64_t gscb[4]; /* guarded storage control */
uint64_t etoken; /* etoken */
uint64_t etoken_extension; /* etoken extension */
@@ -114,6 +113,10 @@ struct CPUS390XState {
uint64_t gbea;
uint64_t pp;
+ /* Fields up to this point are not cleared by normal CPU reset */
+ struct {} start_normal_reset_fields;
+ uint8_t riccb[64]; /* runtime instrumentation control */
+
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
@@ -252,6 +255,7 @@ extern const VMStateDescription vmstate_s390_cpu;
#undef PSW_SHIFT_ASC
#undef PSW_MASK_CC
#undef PSW_MASK_PM
+#undef PSW_MASK_RI
#undef PSW_SHIFT_MASK_PM
#undef PSW_MASK_64
#undef PSW_MASK_32
@@ -273,6 +277,7 @@ extern const VMStateDescription vmstate_s390_cpu;
#define PSW_MASK_CC 0x0000300000000000ULL
#define PSW_MASK_PM 0x00000F0000000000ULL
#define PSW_SHIFT_MASK_PM 40
+#define PSW_MASK_RI 0x0000008000000000ULL
#define PSW_MASK_64 0x0000000100000000ULL
#define PSW_MASK_32 0x0000000080000000ULL
#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL