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Thu, 19 Dec 2019 13:09:39 +0000 From: Klaus Jensen To: Subject: [PATCH v4 09/24] nvme: add temperature threshold feature Date: Thu, 19 Dec 2019 14:09:06 +0100 Message-ID: <20191219130921.309264-10-k.jensen@samsung.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191219130921.309264-1-k.jensen@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA02SXUhTcRjG+e+cnR1Hk9MUfFNDmmgYZYkShxylILHLbgyJhk096mqbY0ct u0mm+YlWZswmfiTmbBHR5pZlGo3IIhGtNMtgjKRm2fIjnUtxbR4N7573fZ7n/f8u/iQmNvAj SaWmmNFpFCoJIcTtr3yjh26VrsmPGK2Itl6rRnSTYxLR3eMM3f45ljZ6qgl6uKEfTyNkFnMt Ifsy+YyQzUxaebLfQxPEKfyMUJrHqJSljO7w8XPCwrHuB7jWGn+pzXODV46ao+tQCAlUCrge mVAdEpJiqheB3rLE44Y/CD4sDuDcsITg3tde/nbFduf+lmFC0O7yYf9TCxtuATeMIOjx3dxy niL46fTygn2CSoDH6348qMOpKKieaOIHQxj1EYFjbVwQNMKodLBbVgNcJIlTcWA0KoJrEZUK c852jOOIAdvK4iZTSGDf1zCNuMxueHN7ZvM+FshU2FoxTgO8cLs3gYAyC2B+8DvBHcqASu8c 4nQY/BjuE3A6GvxPOnhcoR5B4/zyVrsFgaHHSwTpIPB044iKk+nw3JvFyVCY+rWbezcUmuwG jFuLoKZKzF2Ph369DV1HscYd1MYd1MYd1J0IM6MIpoRVFzBssoa5mMgq1GyJpiAxt0htQYHv 8nZjeLkfDa3nOBBFIskuUVr+mlzMV5SyZWoHAhKThIuma3xysShPUXaZ0RVl60pUDOtAUSQu iRAld83KxVSBopi5wDBaRrft8siQyHKk7hB3vZy92tX6Or/hbptUcl55YuVKdnEm7dqLPSyL S8pV6t9p9dHuo/565+zYuJKeapa6UpNM0o33RdNVWTl7Kvd5eirnTw+uns2oT/hr8H86ZvbY nZ0Gcj9/6GBLMy/vJDJV6HrTRyMXhI4UIlXKZkZpY2r98YMxA99atRKcLVQkHcB0rOIfJ2qU lioDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRmVeSWpSXmKPExsVy+t/xu7pTyn7HGkydpmSxub+d0WLSoWuM FksuplrMu6VsMetdO5vF8d4dLA5sHptWdbJ53Lm2h83jybXNTB7v911lC2CJ0rMpyi8tSVXI yC8usVWKNrQw0jO0tNAzMrHUMzQ2j7UyMlXSt7NJSc3JLEst0rdL0Mu4sGQtS8FmtYq57yYy NTBOkeli5OSQEDCR2LpwNUsXIxeHkMBSRok3P16wQiRkJD5d+cgOYQtL/LnWxQZR9JFRYtqH NijnDKPEjZMv2SGcXYwSs5pWM4K0sAloSmz/858FxBYRkJZovzqJFaSIWeA6o8Sh3xfB5goL OEps2/QDqIGDg0VAVWLWrESQMK+AtcSb+/OYIVbLS2z99gnsJE6g+Jbe22DzhQSsJB7//MgC US8ocXLmEzCbGai+eetsZghbQuLgixfMExiFZyEpm4WkbBaSsgWMzKsYRVJLi3PTc4sN9YoT c4tL89L1kvNzNzECY2zbsZ+bdzBe2hh8iFGAg1GJh/dl8u9YIdbEsuLK3EOMEhzMSiK8tzt+ xgrxpiRWVqUW5ccXleakFh9iNAX6bSKzlGhyPjD+80riDU0NzS0sDc2NzY3NLJTEeTsEDsYI CaQnlqRmp6YWpBbB9DFxcEo1MC7SvTbl0Zd/fI3pnxUzqjzOhxxKnRwVeP7Y49tPBOrDCt+X XtjxcMWl/gS9gqudF73t/W5slNwWv9svNe20x4HkX/aexeaJK1cZcQvKfexa5X9d/zmT51ov u9pam+ZzG5hEi4Q5cheu+zlHvnAHr+uBtUuTztvoxZzx9xVwZA+qkBGPP+XtocRSnJFoqMVc VJwIADCn7z3HAgAA X-CMS-MailID: 20191219130940eucas1p2ed4053766595fbef6b5ddee13565f22f X-Msg-Generator: CA X-RootMTR: 20191219130940eucas1p2ed4053766595fbef6b5ddee13565f22f X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191219130940eucas1p2ed4053766595fbef6b5ddee13565f22f References: <20191219130921.309264-1-k.jensen@samsung.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 210.118.77.12 X-Mailman-Approved-At: Thu, 19 Dec 2019 08:56:47 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , qemu-devel@nongnu.org, Max Reitz , Keith Busch , Javier Gonzalez Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" It might seem wierd to implement this feature for an emulated device, but it is mandatory to support and the feature is useful for testing asynchronous event request support, which will be added in a later patch. Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 47 ++++++++++++++++++++++++++++++++++++++++++++ hw/block/nvme.h | 2 ++ include/block/nvme.h | 7 ++++++- 3 files changed, 55 insertions(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index f9b9344f1376..13d412d76c8e 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -45,6 +45,7 @@ #define NVME_SPEC_VER 0x00010201 #define NVME_MAX_QS PCI_MSIX_FLAGS_QSIZE +#define NVME_TEMPERATURE 0x143 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ @@ -801,6 +802,27 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) uint32_t result; switch (dw10) { + case NVME_TEMPERATURE_THRESHOLD: + result = 0; + + /* + * The controller only implements the Composite Temperature sensor, so + * return 0 for all other sensors. + */ + if (NVME_TEMP_TMPSEL(dw10)) { + break; + } + + switch (NVME_TEMP_THSEL(dw10)) { + case 0x0: + result = cpu_to_le16(n->features.temp_thresh_hi); + break; + case 0x1: + result = cpu_to_le16(n->features.temp_thresh_low); + break; + } + + break; case NVME_VOLATILE_WRITE_CACHE: result = blk_enable_write_cache(n->conf.blk); trace_nvme_dev_getfeat_vwcache(result ? "enabled" : "disabled"); @@ -845,6 +867,23 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) uint32_t dw11 = le32_to_cpu(cmd->cdw11); switch (dw10) { + case NVME_TEMPERATURE_THRESHOLD: + if (NVME_TEMP_TMPSEL(dw11)) { + break; + } + + switch (NVME_TEMP_THSEL(dw11)) { + case 0x0: + n->features.temp_thresh_hi = NVME_TEMP_TMPTH(dw11); + break; + case 0x1: + n->features.temp_thresh_low = NVME_TEMP_TMPTH(dw11); + break; + default: + return NVME_INVALID_FIELD | NVME_DNR; + } + + break; case NVME_VOLATILE_WRITE_CACHE: blk_set_enable_write_cache(n->conf.blk, dw11 & 1); break; @@ -1366,6 +1405,9 @@ static void nvme_init_state(NvmeCtrl *n) n->namespaces = g_new0(NvmeNamespace, n->num_namespaces); n->sq = g_new0(NvmeSQueue *, n->params.num_queues); n->cq = g_new0(NvmeCQueue *, n->params.num_queues); + + n->temperature = NVME_TEMPERATURE; + n->features.temp_thresh_hi = le16_to_cpu(n->id_ctrl.wctemp); } static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) @@ -1447,6 +1489,11 @@ static void nvme_init_ctrl(NvmeCtrl *n) id->acl = 3; id->frmw = 7 << 1; id->lpa = 1 << 0; + + /* recommended default value (~70 C) */ + id->wctemp = cpu_to_le16(0x157); + id->cctemp = cpu_to_le16(0x175); + id->sqes = (0x6 << 4) | 0x6; id->cqes = (0x4 << 4) | 0x4; id->nn = cpu_to_le32(n->num_namespaces); diff --git a/hw/block/nvme.h b/hw/block/nvme.h index a867bdfabafd..1518f32557a3 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -108,6 +108,7 @@ typedef struct NvmeCtrl { uint64_t irq_status; uint64_t host_timestamp; /* Timestamp sent by the host */ uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */ + uint16_t temperature; NvmeNamespace *namespaces; NvmeSQueue **sq; @@ -115,6 +116,7 @@ typedef struct NvmeCtrl { NvmeSQueue admin_sq; NvmeCQueue admin_cq; NvmeIdCtrl id_ctrl; + NvmeFeatureVal features; } NvmeCtrl; static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns) diff --git a/include/block/nvme.h b/include/block/nvme.h index d2f65e8fe496..ff31cb32117c 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -616,7 +616,8 @@ enum NvmeIdCtrlOncs { typedef struct NvmeFeatureVal { uint32_t arbitration; uint32_t power_mgmt; - uint32_t temp_thresh; + uint16_t temp_thresh_hi; + uint16_t temp_thresh_low; uint32_t err_rec; uint32_t volatile_wc; uint32_t num_queues; @@ -635,6 +636,10 @@ typedef struct NvmeFeatureVal { #define NVME_INTC_THR(intc) (intc & 0xff) #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) +#define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) +#define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) +#define NVME_TEMP_TMPTH(temp) (temp & 0xffff) + enum NvmeFeatureIds { NVME_ARBITRATION = 0x1, NVME_POWER_MANAGEMENT = 0x2,