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Thu, 19 Dec 2019 13:09:40 +0000 From: Klaus Jensen To: Subject: [PATCH v4 11/24] nvme: add support for the asynchronous event request command Date: Thu, 19 Dec 2019 14:09:08 +0100 Message-ID: <20191219130921.309264-12-k.jensen@samsung.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191219130921.309264-1-k.jensen@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBKsWRmVeSWpSXmKPExsWy7djPc7rTyn7HGrQ947bY3N/OaDHp0DVG iyUXUy3m3VK2mPWunc3ieO8OFgc2j02rOtk87lzbw+bx5NpmJo/3+66yBbBEcdmkpOZklqUW 6dslcGVsf7yctWBaecXjP2/YGhhnR3QxcnJICJhIfPyygbmLkYtDSGAFo8SFE3vZIZwvjBIX 52xkhHA+M0qcfdvMDtPSceAhE0RiOaPE9YdP2eGqJu66A5U5wyix99lhVghnF6PE1a9/2UD6 2QQ0Jbb/+c8CYosISEu0X50EVsQscJ1R4tDvi2BLhAUiJNad+sAMYrMIqErc/nIUrIFXwFri 8ckLzBCHyEts/faJFcTmBIpv6b3NCFEjKHFy5hOwemagmuats5khbAmJgy9egP0qIbCKXeJ+ 316gWzmAHBeJUzskIGYKS7w6vgXqURmJ/zvnM0HUdzNK9H34CtU8g1Fi+rLvbBDN1hJ9Z3Ig GhwltjWcZIUI80nceCsIsZdPYtK26cwQYV6JjjYhiGo1iR1NWxknMCrPQnL1LCRXz0Jy9QJG 5lWM4qmlxbnpqcVGeanlesWJucWleel6yfm5mxiB6eX0v+NfdjDu+pN0iFGAg1GJh/dF8u9Y IdbEsuLK3EOMEhzMSiK8tzt+xgrxpiRWVqUW5ccXleakFh9ilOZgURLnNV70MlZIID2xJDU7 NbUgtQgmy8TBKdXAWLrTQytr3+znJS8dGbnvvOjmX1AQc0Gt1d/+e5DUE66peqtz+Ko7T07j mMUjEaAkE7BmW45O9J4YiV67BUIJvPM+XWW8on0qa24Ry562Rub53xpmnXlonXzpm3Faz8y4 vzseF2aKTyrKmfXmLPv+9Z9zFT/WXtp0uGHbAx/PYzP+Hb1XUj/VT4mlOCPRUIu5qDgRAMkj C2grAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRmVeSWpSXmKPExsVy+t/xe7pTy37HGnxdZGaxub+d0WLSoWuM FksuplrMu6VsMetdO5vF8d4dLA5sHptWdbJ53Lm2h83jybXNTB7v911lC2CJ0rMpyi8tSVXI yC8usVWKNrQw0jO0tNAzMrHUMzQ2j7UyMlXSt7NJSc3JLEst0rdL0MvY/ng5a8G08orHf96w NTDOjuhi5OSQEDCR6DjwkKmLkYtDSGApo8SrvysYIRIyEp+ufGSHsIUl/lzrYoMo+sgosXLW XnYI5wyjxJ/Nu5hBqoQEdjFK/PuXBGKzCWhKbP/znwXEFhGQlmi/OokVpIFZ4DqjxKHfF8HG CguESWyY2csEYrMIqErc/nIUrIFXwFri8ckLzBCr5SW2fvvECmJzAsW39N5mhFhmJfH450eo ekGJkzOfgNnMQPXNW2czQ9gSEgdfvGCewCg8C0nZLCRls5CULWBkXsUoklpanJueW2yoV5yY W1yal66XnJ+7iREYY9uO/dy8g/HSxuBDjAIcjEo8vC+Tf8cKsSaWFVfmHmKU4GBWEuG93fEz Vog3JbGyKrUoP76oNCe1+BCjKdBzE5mlRJPzgfGfVxJvaGpobmFpaG5sbmxmoSTO2yFwMEZI ID2xJDU7NbUgtQimj4mDU6qBsT/y9u9Zh+Z0C6wr+23d6Z3aH7acna9vB1e7bYifcs636pNR 5go52jfWtW568+B1VOOCtB8Sk3OzJjz70VTE/+HbpJ8/dkftsEwQ4P/Ce+3PO01RIeHt19YV 7ZE1EKk4fei0Hk+rhuJHy7XLDlpYllgvrGic4BkVpaBS9qp3rtlPYaVrx7ZlKbEUZyQaajEX FScCAP7AmRTHAgAA X-CMS-MailID: 20191219130941eucas1p1ac686ade1ad42395500069d8884f9179 X-Msg-Generator: CA X-RootMTR: 20191219130941eucas1p1ac686ade1ad42395500069d8884f9179 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191219130941eucas1p1ac686ade1ad42395500069d8884f9179 References: <20191219130921.309264-1-k.jensen@samsung.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 210.118.77.12 X-Mailman-Approved-At: Thu, 19 Dec 2019 08:56:47 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , qemu-devel@nongnu.org, Max Reitz , Keith Busch , Javier Gonzalez Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Required for compliance with NVMe revision 1.2.1. See NVM Express 1.2.1, Section 5.2 ("Asynchronous Event Request command"). Mostly imported from Keith's qemu-nvme tree. Modified with a max number of queued events (controllable with the aer_max_queued device parameter). The spec states that the controller *should* retain events, so we do best effort here. Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 167 +++++++++++++++++++++++++++++++++++++++++- hw/block/nvme.h | 14 +++- hw/block/trace-events | 9 +++ include/block/nvme.h | 8 +- 4 files changed, 191 insertions(+), 7 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 38a555c047d3..113b64ea1843 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -323,6 +323,85 @@ static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req) timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); } +static void nvme_process_aers(void *opaque) +{ + NvmeCtrl *n = opaque; + NvmeAsyncEvent *event, *next; + + trace_nvme_dev_process_aers(n->aer_queued); + + QTAILQ_FOREACH_SAFE(event, &n->aer_queue, entry, next) { + NvmeRequest *req; + NvmeAerResult *result; + + /* can't post cqe if there is nothing to complete */ + if (!n->outstanding_aers) { + trace_nvme_dev_no_outstanding_aers(); + break; + } + + /* ignore if masked (cqe posted, but event not cleared) */ + if (n->aer_mask & (1 << event->result.event_type)) { + trace_nvme_dev_aer_masked(event->result.event_type, n->aer_mask); + continue; + } + + QTAILQ_REMOVE(&n->aer_queue, event, entry); + n->aer_queued--; + + n->aer_mask |= 1 << event->result.event_type; + n->outstanding_aers--; + + req = n->aer_reqs[n->outstanding_aers]; + + result = (NvmeAerResult *) &req->cqe.result; + result->event_type = event->result.event_type; + result->event_info = event->result.event_info; + result->log_page = event->result.log_page; + g_free(event); + + req->status = NVME_SUCCESS; + + trace_nvme_dev_aer_post_cqe(result->event_type, result->event_info, + result->log_page); + + nvme_enqueue_req_completion(&n->admin_cq, req); + } +} + +static void nvme_enqueue_event(NvmeCtrl *n, uint8_t event_type, + uint8_t event_info, uint8_t log_page) +{ + NvmeAsyncEvent *event; + + trace_nvme_dev_enqueue_event(event_type, event_info, log_page); + + if (n->aer_queued == n->params.aer_max_queued) { + trace_nvme_dev_enqueue_event_noqueue(n->aer_queued); + return; + } + + event = g_new(NvmeAsyncEvent, 1); + event->result = (NvmeAerResult) { + .event_type = event_type, + .event_info = event_info, + .log_page = log_page, + }; + + QTAILQ_INSERT_TAIL(&n->aer_queue, event, entry); + n->aer_queued++; + + nvme_process_aers(n); +} + +static void nvme_clear_events(NvmeCtrl *n, uint8_t event_type) +{ + n->aer_mask &= ~(1 << event_type); + if (!QTAILQ_EMPTY(&n->aer_queue)) { + nvme_process_aers(n); + } +} + static void nvme_rw_cb(void *opaque, int ret) { NvmeRequest *req = opaque; @@ -567,8 +646,8 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd) return NVME_SUCCESS; } -static uint16_t nvme_smart_info(NvmeCtrl *n, NvmeCmd *cmd, uint32_t buf_len, - uint64_t off, NvmeRequest *req) +static uint16_t nvme_smart_info(NvmeCtrl *n, NvmeCmd *cmd, uint8_t rae, + uint32_t buf_len, uint64_t off, NvmeRequest *req) { uint64_t prp1 = le64_to_cpu(cmd->prp1); uint64_t prp2 = le64_to_cpu(cmd->prp2); @@ -617,6 +696,10 @@ static uint16_t nvme_smart_info(NvmeCtrl *n, NvmeCmd *cmd, uint32_t buf_len, smart.power_on_hours[0] = cpu_to_le64( (((current_ms - n->starttime_ms) / 1000) / 60) / 60); + if (!rae) { + nvme_clear_events(n, NVME_AER_TYPE_SMART); + } + return nvme_dma_read_prp(n, (uint8_t *) &smart + off, trans_len, prp1, prp2); } @@ -669,13 +752,17 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) switch (lid) { case NVME_LOG_ERROR_INFO: + if (!rae) { + nvme_clear_events(n, NVME_AER_TYPE_ERROR); + } + if (off) { return NVME_INVALID_FIELD | NVME_DNR; } return NVME_SUCCESS; case NVME_LOG_SMART_INFO: - return nvme_smart_info(n, cmd, len, off, req); + return nvme_smart_info(n, cmd, rae, len, off, req); case NVME_LOG_FW_SLOT_INFO: return nvme_fw_log_info(n, cmd, len, off, req); default: @@ -951,6 +1038,9 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) break; case NVME_TIMESTAMP: return nvme_get_feature_timestamp(n, cmd); + case NVME_ASYNCHRONOUS_EVENT_CONF: + result = cpu_to_le32(n->features.async_config); + break; default: trace_nvme_dev_err_invalid_getfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; @@ -1000,6 +1090,13 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) return NVME_INVALID_FIELD | NVME_DNR; } + if (((n->temperature > n->features.temp_thresh_hi) || + (n->temperature < n->features.temp_thresh_low)) && + NVME_AEC_SMART(n->features.async_config) & NVME_SMART_TEMPERATURE) { + nvme_enqueue_event(n, NVME_AER_TYPE_SMART, + NVME_AER_INFO_SMART_TEMP_THRESH, NVME_LOG_SMART_INFO); + } + break; case NVME_VOLATILE_WRITE_CACHE: blk_set_enable_write_cache(n->conf.blk, dw11 & 1); @@ -1013,6 +1110,9 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); + case NVME_ASYNCHRONOUS_EVENT_CONF: + n->features.async_config = dw11; + break; default: trace_nvme_dev_err_invalid_setfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; @@ -1021,6 +1121,25 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) return NVME_SUCCESS; } +static uint16_t nvme_aer(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) +{ + trace_nvme_dev_aer(nvme_cid(req)); + + if (n->outstanding_aers > n->params.aerl) { + trace_nvme_dev_aer_aerl_exceeded(); + return NVME_AER_LIMIT_EXCEEDED; + } + + n->aer_reqs[n->outstanding_aers] = req; + n->outstanding_aers++; + + if (!QTAILQ_EMPTY(&n->aer_queue)) { + nvme_process_aers(n); + } + + return NVME_NO_COMPLETE; +} + static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) { switch (cmd->opcode) { @@ -1042,6 +1161,8 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) return nvme_set_feature(n, cmd, req); case NVME_ADM_CMD_GET_FEATURES: return nvme_get_feature(n, cmd, req); + case NVME_ADM_CMD_ASYNC_EV_REQ: + return nvme_aer(n, cmd, req); default: trace_nvme_dev_err_invalid_admin_opc(cmd->opcode); return NVME_INVALID_OPCODE | NVME_DNR; @@ -1096,6 +1217,15 @@ static void nvme_clear_ctrl(NvmeCtrl *n) } } + while (!QTAILQ_EMPTY(&n->aer_queue)) { + NvmeAsyncEvent *event = QTAILQ_FIRST(&n->aer_queue); + QTAILQ_REMOVE(&n->aer_queue, event, entry); + g_free(event); + } + + n->aer_queued = 0; + n->outstanding_aers = 0; + blk_flush(n->conf.blk); n->bar.cc = 0; } @@ -1192,6 +1322,8 @@ static int nvme_start_ctrl(NvmeCtrl *n) nvme_set_timestamp(n, 0ULL); + QTAILQ_INIT(&n->aer_queue); + return 0; } @@ -1384,6 +1516,13 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) "completion queue doorbell write" " for nonexistent queue," " sqid=%"PRIu32", ignoring", qid); + + if (n->outstanding_aers) { + nvme_enqueue_event(n, NVME_AER_TYPE_ERROR, + NVME_AER_INFO_ERR_INVALID_DB_REGISTER, + NVME_LOG_ERROR_INFO); + } + return; } @@ -1394,6 +1533,12 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) " beyond queue size, sqid=%"PRIu32"," " new_head=%"PRIu16", ignoring", qid, new_head); + + if (n->outstanding_aers) { + nvme_enqueue_event(n, NVME_AER_TYPE_ERROR, + NVME_AER_INFO_ERR_INVALID_DB_VALUE, NVME_LOG_ERROR_INFO); + } + return; } @@ -1422,6 +1567,13 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) "submission queue doorbell write" " for nonexistent queue," " sqid=%"PRIu32", ignoring", qid); + + if (n->outstanding_aers) { + nvme_enqueue_event(n, NVME_AER_TYPE_ERROR, + NVME_AER_INFO_ERR_INVALID_DB_REGISTER, + NVME_LOG_ERROR_INFO); + } + return; } @@ -1432,6 +1584,12 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) " beyond queue size, sqid=%"PRIu32"," " new_tail=%"PRIu16", ignoring", qid, new_tail); + + if (n->outstanding_aers) { + nvme_enqueue_event(n, NVME_AER_TYPE_ERROR, + NVME_AER_INFO_ERR_INVALID_DB_VALUE, NVME_LOG_ERROR_INFO); + } + return; } @@ -1528,6 +1686,7 @@ static void nvme_init_state(NvmeCtrl *n) n->temperature = NVME_TEMPERATURE; n->features.temp_thresh_hi = le16_to_cpu(n->id_ctrl.wctemp); n->starttime_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); + n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1); } static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) @@ -1607,6 +1766,7 @@ static void nvme_init_ctrl(NvmeCtrl *n) * inconsequential. */ id->acl = 3; + id->aerl = n->params.aerl; id->frmw = 7 << 1; id->lpa = 1 << 2; @@ -1697,6 +1857,7 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->namespaces); g_free(n->cq); g_free(n->sq); + g_free(n->aer_reqs); if (n->params.cmb_size_mb) { g_free(n->cmbuf); diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 89b0aafa02a2..1e715ab1d75c 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -6,16 +6,20 @@ #define DEFINE_NVME_PROPERTIES(_state, _props) \ DEFINE_PROP_STRING("serial", _state, _props.serial), \ DEFINE_PROP_UINT32("cmb_size_mb", _state, _props.cmb_size_mb, 0), \ - DEFINE_PROP_UINT32("num_queues", _state, _props.num_queues, 64) + DEFINE_PROP_UINT32("num_queues", _state, _props.num_queues, 64), \ + DEFINE_PROP_UINT8("aerl", _state, _props.aerl, 3), \ + DEFINE_PROP_UINT32("aer_max_queued", _state, _props.aer_max_queued, 64) typedef struct NvmeParams { char *serial; uint32_t num_queues; uint32_t cmb_size_mb; + uint8_t aerl; + uint32_t aer_max_queued; } NvmeParams; typedef struct NvmeAsyncEvent { - QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry; + QTAILQ_ENTRY(NvmeAsyncEvent) entry; NvmeAerResult result; } NvmeAsyncEvent; @@ -102,6 +106,7 @@ typedef struct NvmeCtrl { uint32_t num_namespaces; uint32_t max_q_ents; uint64_t ns_size; + uint8_t outstanding_aers; uint32_t cmbsz; uint32_t cmbloc; uint8_t *cmbuf; @@ -111,6 +116,11 @@ typedef struct NvmeCtrl { uint16_t temperature; uint64_t starttime_ms; + uint8_t aer_mask; + NvmeRequest **aer_reqs; + QTAILQ_HEAD(, NvmeAsyncEvent) aer_queue; + int aer_queued; + NvmeNamespace *namespaces; NvmeSQueue **sq; NvmeCQueue **cq; diff --git a/hw/block/trace-events b/hw/block/trace-events index 7da088479f39..3952c36774cf 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -47,6 +47,15 @@ nvme_dev_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested cq_ nvme_dev_setfeat_timestamp(uint64_t ts) "set feature timestamp = 0x%"PRIx64"" nvme_dev_getfeat_timestamp(uint64_t ts) "get feature timestamp = 0x%"PRIx64"" nvme_dev_get_log(uint16_t cid, uint8_t lid, uint8_t rae, uint32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" rae 0x%"PRIx8" len %"PRIu32" off %"PRIu64"" +nvme_dev_process_aers(int queued) "queued %d" +nvme_dev_aer(uint16_t cid) "cid %"PRIu16"" +nvme_dev_aer_aerl_exceeded(void) "aerl exceeded" +nvme_dev_aer_masked(uint8_t type, uint8_t mask) "type 0x%"PRIx8" mask 0x%"PRIx8"" +nvme_dev_aer_post_cqe(uint8_t typ, uint8_t info, uint8_t log_page) "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" +nvme_dev_enqueue_event(uint8_t typ, uint8_t info, uint8_t log_page) "type 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" +nvme_dev_enqueue_event_noqueue(int queued) "queued %d" +nvme_dev_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" +nvme_dev_no_outstanding_aers(void) "ignoring event; no outstanding AERs" nvme_dev_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask set, data=0x%"PRIx64", new_mask=0x%"PRIx64"" nvme_dev_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask clr, data=0x%"PRIx64", new_mask=0x%"PRIx64"" nvme_dev_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=0x%"PRIx64"" diff --git a/include/block/nvme.h b/include/block/nvme.h index 9a6055adeb61..a24be047a311 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -386,8 +386,8 @@ enum NvmeAsyncEventRequest { NVME_AER_TYPE_SMART = 1, NVME_AER_TYPE_IO_SPECIFIC = 6, NVME_AER_TYPE_VENDOR_SPECIFIC = 7, - NVME_AER_INFO_ERR_INVALID_SQ = 0, - NVME_AER_INFO_ERR_INVALID_DB = 1, + NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, + NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, NVME_AER_INFO_ERR_DIAG_FAIL = 2, NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, @@ -640,6 +640,10 @@ typedef struct NvmeFeatureVal { #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) +#define NVME_AEC_SMART(aec) (aec & 0xff) +#define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) +#define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) + enum NvmeFeatureIds { NVME_ARBITRATION = 0x1, NVME_POWER_MANAGEMENT = 0x2,