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Thu, 19 Dec 2019 13:09:43 +0000 From: Klaus Jensen To: Subject: [PATCH v4 15/24] nvme: bump supported specification to 1.3 Date: Thu, 19 Dec 2019 14:09:12 +0100 Message-ID: <20191219130921.309264-16-k.jensen@samsung.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191219130921.309264-1-k.jensen@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOKsWRmVeSWpSXmKPExsWy7djPc7ozy37HGhz4x2yxub+d0WLSoWuM FksuplrMu6VsMetdO5vF8d4dLA5sHptWdbJ53Lm2h83jybXNTB7v911lC2CJ4rJJSc3JLEst 0rdL4Mp4tOokS8F3x4qvC5axNDD+MOxi5OSQEDCRuHPwOVsXIxeHkMAKRokPJ1ayQDhfGCV+ /OyBcj4zShzZe4EdpuX2loPMEInljBJnHm9kAUmAVXXt84JInGGU2LjyBlTVLkaJP31nWUGq 2AQ0Jbb/+Q/WISIgLdF+dRIrSBGzwHVGiUO/L4LtEBZwlug61gNmswioSpya0MAEYvMKWEtc PbuTDeIOeYmt3z6BDeUEim/pvc0IUSMocXLmE7AFzEA1zVtnM0PYEhIHX7xghuhdxS6xfFsW hO0isWbCCkYIW1ji1fEtUH/KSPzfOZ8J5DgJgW5Gib4PX5khnBmMEtOXfQe6ggPIsZboO5MD 0eAo8fLODnaIMJ/EjbeCEHv5JCZtm84MEeaV6GgTgqhWk9jRtJVxAqPyLCRXz0Jy9SwkVy9g ZF7FKJ5aWpybnlpsnJdarlecmFtcmpeul5yfu4kRmFxO/zv+dQfjvj9JhxgFOBiVeHgd0n7H CrEmlhVX5h5ilOBgVhLhvd3xM1aINyWxsiq1KD++qDQntfgQozQHi5I4r/Gil7FCAumJJanZ qakFqUUwWSYOTqkGRuFEfq37G8seVLK51KzjLf25b73HZbunh9qyfgQ73IwVzP/zNeqrqula aVPfDu/prVfXPO585T/pwUfjthLrQ3Ynt+3RDxA8dIEl2N/12tQgi4s3psgEsc8z3+q/hzdX VTrDQdt01vJ1V/sUjx/pXzWDi+Gllh/nxRpe5XOLlj06tfv8J1Pxu0osxRmJhlrMRcWJANBO 6YEqAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRmVeSWpSXmKPExsVy+t/xu7ozyn7HGiw7qWmxub+d0WLSoWuM FksuplrMu6VsMetdO5vF8d4dLA5sHptWdbJ53Lm2h83jybXNTB7v911lC2CJ0rMpyi8tSVXI yC8usVWKNrQw0jO0tNAzMrHUMzQ2j7UyMlXSt7NJSc3JLEst0rdL0Mt4tOokS8F3x4qvC5ax NDD+MOxi5OSQEDCRuL3lIHMXIxeHkMBSRonlH/cyQiRkJD5d+cgOYQtL/LnWxQZR9JFR4lLD J2aQhJDAGUaJSQs4IRK7GCVOvN3OBJJgE9CU2P7nPwuILSIgLdF+dRIrSBGzwHVGiUO/L4KN FRZwlug61gNmswioSpya0ADWzCtgLXH17E42iNXyElu/fWIFsTmB4lt6bzNCbLaSePzzIwtE vaDEyZlPwGxmoPrmrbOZIWwJiYMvXjBPYBSehaRsFpKyWUjKFjAyr2IUSS0tzk3PLTbSK07M LS7NS9dLzs/dxAiMsW3Hfm7Zwdj1LvgQowAHoxIPr0Pa71gh1sSy4srcQ4wSHMxKIry3O37G CvGmJFZWpRblxxeV5qQWH2I0BXpuIrOUaHI+MP7zSuINTQ3NLSwNzY3Njc0slMR5OwQOxggJ pCeWpGanphakFsH0MXFwSjUwWoisbREue/5SU5EtN/fxyZJbTnelltdqHRc2uroo94ht2u49 2tfr9za47V36s1A3KODwKwOzE+J7vjx1k+awUBQ0ea4ZN6fdbNV9cYGXO54YLtgpXXNi0+Tb oh+UnmVxr/zq5yxymW/DtmixjXZiX57W3a/bqLlEMPVL+es5fNKi+xUNxXZvU2Ipzkg01GIu Kk4EAJNOm1/HAgAA X-CMS-MailID: 20191219130944eucas1p1c2c335692dc0a44467e33afa6aa5e558 X-Msg-Generator: CA X-RootMTR: 20191219130944eucas1p1c2c335692dc0a44467e33afa6aa5e558 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20191219130944eucas1p1c2c335692dc0a44467e33afa6aa5e558 References: <20191219130921.309264-1-k.jensen@samsung.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 210.118.77.12 X-Mailman-Approved-At: Thu, 19 Dec 2019 08:56:47 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , qemu-devel@nongnu.org, Max Reitz , Keith Busch , Javier Gonzalez Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Add new fields to the Identify Controller and Identify Namespace data structures accoding to NVM Express 1.3d. NVM Express 1.3d requires the following additional features: - addition of the Namespace Identification Descriptor List (CNS 03h) for the Identify command - support for returning Command Sequence Error if a Set Features command is submitted for the Number of Queues feature after any I/O queues have been created. - The addition of the Log Specific Field (LSP) in the Get Log Page command. Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 57 ++++++++++++++++++++++++++++++++++++++++--- hw/block/nvme.h | 1 + hw/block/trace-events | 3 ++- include/block/nvme.h | 20 ++++++++++----- 4 files changed, 71 insertions(+), 10 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 040dec234714..6d942c47ce58 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -9,7 +9,7 @@ */ /** - * Reference Specification: NVM Express 1.2.1 + * Reference Specification: NVM Express 1.3d * * https://nvmexpress.org/resources/specifications/ */ @@ -43,7 +43,7 @@ #include "trace.h" #include "nvme.h" -#define NVME_SPEC_VER 0x00010201 +#define NVME_SPEC_VER 0x00010300 #define NVME_MAX_QS PCI_MSIX_FLAGS_QSIZE #define NVME_TEMPERATURE 0x143 @@ -733,6 +733,7 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) uint32_t dw12 = le32_to_cpu(cmd->cdw12); uint32_t dw13 = le32_to_cpu(cmd->cdw13); uint8_t lid = dw10 & 0xff; + uint8_t lsp = (dw10 >> 8) & 0xf; uint8_t rae = (dw10 >> 15) & 0x1; uint32_t numdl, numdu; uint64_t off, lpol, lpou; @@ -750,7 +751,7 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) return NVME_INVALID_FIELD | NVME_DNR; } - trace_nvme_dev_get_log(nvme_cid(req), lid, rae, len, off); + trace_nvme_dev_get_log(nvme_cid(req), lid, lsp, rae, len, off); switch (lid) { case NVME_LOG_ERROR_INFO: @@ -861,6 +862,8 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd) cq = g_malloc0(sizeof(*cq)); nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1, NVME_CQ_FLAGS_IEN(qflags)); + + n->qs_created = true; return NVME_SUCCESS; } @@ -922,6 +925,47 @@ static uint16_t nvme_identify_ns_list(NvmeCtrl *n, NvmeIdentify *c) return ret; } +static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeCmd *c) +{ + static const int len = 4096; + + struct ns_descr { + uint8_t nidt; + uint8_t nidl; + uint8_t rsvd2[2]; + uint8_t nid[16]; + }; + + uint32_t nsid = le32_to_cpu(c->nsid); + uint64_t prp1 = le64_to_cpu(c->prp1); + uint64_t prp2 = le64_to_cpu(c->prp2); + + struct ns_descr *list; + uint16_t ret; + + trace_nvme_dev_identify_ns_descr_list(nsid); + + if (unlikely(nsid == 0 || nsid > n->num_namespaces)) { + trace_nvme_dev_err_invalid_ns(nsid, n->num_namespaces); + return NVME_INVALID_NSID | NVME_DNR; + } + + /* + * Because the NGUID and EUI64 fields are 0 in the Identify Namespace data + * structure, a Namespace UUID (nidt = 0x3) must be reported in the + * Namespace Identification Descriptor. Add a very basic Namespace UUID + * here. + */ + list = g_malloc0(len); + list->nidt = 0x3; + list->nidl = 0x10; + *(uint32_t *) &list->nid[12] = cpu_to_be32(nsid); + + ret = nvme_dma_read_prp(n, (uint8_t *) list, len, prp1, prp2); + g_free(list); + return ret; +} + static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd) { NvmeIdentify *c = (NvmeIdentify *)cmd; @@ -933,6 +977,8 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd) return nvme_identify_ctrl(n, c); case 0x02: return nvme_identify_ns_list(n, c); + case 0x03: + return nvme_identify_ns_descr_list(n, cmd); default: trace_nvme_dev_err_invalid_identify_cns(le32_to_cpu(c->cns)); return NVME_INVALID_FIELD | NVME_DNR; @@ -1131,6 +1177,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) blk_set_enable_write_cache(n->conf.blk, dw11 & 1); break; case NVME_NUMBER_OF_QUEUES: + if (n->qs_created) { + return NVME_CMD_SEQ_ERROR | NVME_DNR; + } + if ((dw11 & 0xffff) == 0xffff || ((dw11 >> 16) & 0xffff) == 0xffff) { return NVME_INVALID_FIELD | NVME_DNR; } @@ -1265,6 +1315,7 @@ static void nvme_clear_ctrl(NvmeCtrl *n) n->aer_queued = 0; n->outstanding_aers = 0; + n->qs_created = false; blk_flush(n->conf.blk); n->bar.cc = 0; diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 1e715ab1d75c..7ced5fd485a9 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -97,6 +97,7 @@ typedef struct NvmeCtrl { BlockConf conf; NvmeParams params; + bool qs_created; uint32_t page_size; uint16_t page_bits; uint16_t max_prp_ents; diff --git a/hw/block/trace-events b/hw/block/trace-events index f982ec1a3221..9e5a4548bde0 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -41,6 +41,7 @@ nvme_dev_del_cq(uint16_t cqid) "deleted completion queue, sqid=%"PRIu16"" nvme_dev_identify_ctrl(void) "identify controller" nvme_dev_identify_ns(uint32_t ns) "nsid %"PRIu32"" nvme_dev_identify_ns_list(uint32_t ns) "nsid %"PRIu32"" +nvme_dev_identify_ns_descr_list(uint32_t ns) "nsid %"PRIu32"" nvme_dev_getfeat(uint16_t cid, uint32_t fid) "cid %"PRIu16" fid 0x%"PRIx32"" nvme_dev_setfeat(uint16_t cid, uint32_t fid, uint32_t val) "cid %"PRIu16" fid 0x%"PRIx32" val 0x%"PRIx32"" nvme_dev_getfeat_vwcache(const char* result) "get feature volatile write cache, result=%s" @@ -48,7 +49,7 @@ nvme_dev_getfeat_numq(int result) "get feature number of queues, result=%d" nvme_dev_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested cq_count=%d sq_count=%d, responding with cq_count=%d sq_count=%d" nvme_dev_setfeat_timestamp(uint64_t ts) "set feature timestamp = 0x%"PRIx64"" nvme_dev_getfeat_timestamp(uint64_t ts) "get feature timestamp = 0x%"PRIx64"" -nvme_dev_get_log(uint16_t cid, uint8_t lid, uint8_t rae, uint32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" rae 0x%"PRIx8" len %"PRIu32" off %"PRIu64"" +nvme_dev_get_log(uint16_t cid, uint8_t lid, uint8_t lsp, uint8_t rae, uint32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" lsp 0x%"PRIx8" rae 0x%"PRIx8" len %"PRIu32" off %"PRIu64"" nvme_dev_process_aers(int queued) "queued %d" nvme_dev_aer(uint16_t cid) "cid %"PRIu16"" nvme_dev_aer_aerl_exceeded(void) "aerl exceeded" diff --git a/include/block/nvme.h b/include/block/nvme.h index 09419ed499d0..31eb9397d8c6 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -550,7 +550,9 @@ typedef struct NvmeIdCtrl { uint32_t rtd3e; uint32_t oaes; uint32_t ctratt; - uint8_t rsvd100[156]; + uint8_t rsvd100[12]; + uint8_t fguid[16]; + uint8_t rsvd128[128]; uint16_t oacs; uint8_t acl; uint8_t aerl; @@ -568,9 +570,15 @@ typedef struct NvmeIdCtrl { uint8_t tnvmcap[16]; uint8_t unvmcap[16]; uint32_t rpmbs; - uint8_t rsvd316[4]; + uint16_t edstt; + uint8_t dsto; + uint8_t fwug; uint16_t kas; - uint8_t rsvd322[190]; + uint16_t hctma; + uint16_t mntmt; + uint16_t mxtmt; + uint32_t sanicap; + uint8_t rsvd332[180]; uint8_t sqes; uint8_t cqes; uint16_t maxcmd; @@ -691,19 +699,19 @@ typedef struct NvmeIdNs { uint8_t rescap; uint8_t fpi; uint8_t dlfeat; - uint8_t rsvd33; uint16_t nawun; uint16_t nawupf; + uint16_t nacwu; uint16_t nabsn; uint16_t nabo; uint16_t nabspf; - uint8_t rsvd46[2]; + uint16_t noiob; uint8_t nvmcap[16]; uint8_t rsvd64[40]; uint8_t nguid[16]; uint64_t eui64; NvmeLBAF lbaf[16]; - uint8_t res192[192]; + uint8_t rsvd192[192]; uint8_t vs[3712]; } NvmeIdNs;