From patchwork Mon Feb 24 14:19:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 11400605 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 013C417D5 for ; Mon, 24 Feb 2020 14:21:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D655D2080D for ; Mon, 24 Feb 2020 14:21:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D655D2080D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:37030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6EcA-0001EZ-0J for patchwork-qemu-devel@patchwork.kernel.org; Mon, 24 Feb 2020 09:21:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:48330) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6Ea6-0004J1-2s for qemu-devel@nongnu.org; Mon, 24 Feb 2020 09:19:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6Ea4-0005pV-6e for qemu-devel@nongnu.org; Mon, 24 Feb 2020 09:19:33 -0500 Received: from mail02.asahi-net.or.jp ([202.224.55.14]:55150) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1j6Ea3-0005oL-V0 for qemu-devel@nongnu.org; Mon, 24 Feb 2020 09:19:32 -0500 Received: from h61-195-96-97.vps.ablenet.jp (h61-195-96-97.ablenetvps.ne.jp [61.195.96.97]) (Authenticated sender: PQ4Y-STU) by mail02.asahi-net.or.jp (Postfix) with ESMTPA id 4D49AE5530; Mon, 24 Feb 2020 23:19:30 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by h61-195-96-97.vps.ablenet.jp (Postfix) with ESMTPSA id 0E00424008F; Mon, 24 Feb 2020 23:19:30 +0900 (JST) From: Yoshinori Sato To: qemu-devel@nongnu.org Subject: [PATCH v32 08/22] target/rx: Disassemble rx_index_addr into a string Date: Mon, 24 Feb 2020 23:19:09 +0900 Message-Id: <20200224141923.82118-9-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224141923.82118-1-ysato@users.sourceforge.jp> References: <20200224141923.82118-1-ysato@users.sourceforge.jp> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 202.224.55.14 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, Richard Henderson , Yoshinori Sato Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We were eliding all zero indexes. It is only ld==0 that does not have an index in the instruction. This also allows us to avoid breaking the final print into multiple pieces. Reviewed-by: Yoshinori Sato Signed-off-by: Yoshinori Sato Message-Id: <20190607091116.49044-19-ysato@users.sourceforge.jp> Tested-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/rx/disas.c | 154 +++++++++++++++++----------------------------- 1 file changed, 55 insertions(+), 99 deletions(-) diff --git a/target/rx/disas.c b/target/rx/disas.c index 8cada4825d..64342537ee 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -107,49 +107,42 @@ static const char psw[] = { 'i', 'u', 0, 0, 0, 0, 0, 0, }; -static uint32_t rx_index_addr(int ld, int size, DisasContext *ctx) +static void rx_index_addr(DisasContext *ctx, char out[8], int ld, int mi) { - bfd_byte buf[2]; + uint32_t addr = ctx->addr; + uint8_t buf[2]; + uint16_t dsp; + switch (ld) { case 0: - return 0; + /* No index; return empty string. */ + out[0] = '\0'; + return; case 1: - ctx->dis->read_memory_func(ctx->addr, buf, 1, ctx->dis); ctx->addr += 1; - return ((uint8_t)buf[0]) << size; + ctx->dis->read_memory_func(addr, buf, 1, ctx->dis); + dsp = buf[0]; + break; case 2: - ctx->dis->read_memory_func(ctx->addr, buf, 2, ctx->dis); ctx->addr += 2; - return lduw_le_p(buf) << size; + ctx->dis->read_memory_func(addr, buf, 2, ctx->dis); + dsp = lduw_le_p(buf); + break; + default: + g_assert_not_reached(); } - g_assert_not_reached(); + + sprintf(out, "%u", dsp << (mi < 3 ? mi : 4 - mi)); } static void operand(DisasContext *ctx, int ld, int mi, int rs, int rd) { - int dsp; static const char sizes[][4] = {".b", ".w", ".l", ".uw", ".ub"}; + char dsp[8]; + if (ld < 3) { - switch (mi) { - case 4: - /* dsp[rs].ub */ - dsp = rx_index_addr(ld, RX_MEMORY_BYTE, ctx); - break; - case 3: - /* dsp[rs].uw */ - dsp = rx_index_addr(ld, RX_MEMORY_WORD, ctx); - break; - default: - /* dsp[rs].b */ - /* dsp[rs].w */ - /* dsp[rs].l */ - dsp = rx_index_addr(ld, mi, ctx); - break; - } - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]%s", rs, sizes[mi]); + rx_index_addr(ctx, dsp, ld, mi); + prt("%s[r%d]%s", dsp, rs, sizes[mi]); } else { prt("r%d", rs); } @@ -235,7 +228,7 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) /* mov.[bwl] rs,rd */ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) { - int dsp; + char dspd[8], dsps[8]; prt("mov.%c\t", size[a->sz]); if (a->lds == 3 && a->ldd == 3) { @@ -244,29 +237,15 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) return true; } if (a->lds == 3) { - prt("r%d, ", a->rd); - dsp = rx_index_addr(a->ldd, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]", a->rs); + rx_index_addr(ctx, dspd, a->ldd, a->sz); + prt("r%d, %s[r%d]", a->rs, dspd, a->rd); } else if (a->ldd == 3) { - dsp = rx_index_addr(a->lds, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d], r%d", a->rs, a->rd); + rx_index_addr(ctx, dsps, a->lds, a->sz); + prt("%s[r%d], r%d", dsps, a->rs, a->rd); } else { - dsp = rx_index_addr(a->lds, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d], ", a->rs); - dsp = rx_index_addr(a->ldd, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]", a->rd); + rx_index_addr(ctx, dsps, a->lds, a->sz); + rx_index_addr(ctx, dspd, a->ldd, a->sz); + prt("%s[r%d], %s[r%d]", dsps, a->rs, dspd, a->rd); } return true; } @@ -357,12 +336,10 @@ static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) /* push dsp[rs] */ static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) { - prt("push\t"); - int dsp = rx_index_addr(a->ld, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]", a->rs); + char dsp[8]; + + rx_index_addr(ctx, dsp, a->ld, a->sz); + prt("push\t%s[r%d]", dsp, a->rs); return true; } @@ -389,17 +366,13 @@ static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) /* xchg dsp[rs].,rd */ static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) { - int dsp; static const char msize[][4] = { "b", "w", "l", "ub", "uw", }; + char dsp[8]; - prt("xchg\t"); - dsp = rx_index_addr(a->ld, a->mi, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d].%s, r%d", a->rs, msize[a->mi], a->rd); + rx_index_addr(ctx, dsp, a->ld, a->mi); + prt("xchg\t%s[r%d].%s, r%d", dsp, a->rs, msize[a->mi], a->rd); return true; } @@ -552,13 +525,10 @@ static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) /* adc dsp[rs], rd */ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) { - int dsp; - prt("adc\t"); - dsp = rx_index_addr(a->ld, 2, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d], r%d", a->rs, a->rd); + char dsp[8]; + + rx_index_addr(ctx, dsp, a->ld, 2); + prt("adc\t%s[r%d], r%d", dsp, a->rs, a->rd); return true; } @@ -1217,25 +1187,17 @@ static bool trans_ITOF(DisasContext *ctx, arg_ITOF *a) #define BOP_IM(name, reg) \ do { \ - int dsp; \ - prt("b%s\t#%d, ", #name, a->imm); \ - dsp = rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); \ - if (dsp > 0) { \ - prt("%d", dsp); \ - } \ - prt("[r%d]", reg); \ + char dsp[8]; \ + rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE); \ + prt("b%s\t#%d, %s[r%d]", #name, a->imm, dsp, reg); \ return true; \ } while (0) #define BOP_RM(name) \ do { \ - int dsp; \ - prt("b%s\tr%d, ", #name, a->rd); \ - dsp = rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); \ - if (dsp > 0) { \ - prt("%d", dsp); \ - } \ - prt("[r%d]", a->rs); \ + char dsp[8]; \ + rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE); \ + prt("b%s\tr%d, %s[r%d]", #name, a->rd, dsp, a->rs); \ return true; \ } while (0) @@ -1346,12 +1308,10 @@ static bool trans_BNOT_ir(DisasContext *ctx, arg_BNOT_ir *a) /* bmcond #imm, dsp[rd] */ static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) { - int dsp = rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); - prt("bm%s\t#%d, ", cond[a->cd], a->imm); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[%d]", a->rd); + char dsp[8]; + + rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE); + prt("bm%s\t#%d, %s[r%d]", cond[a->cd], a->imm, dsp, a->rd); return true; } @@ -1443,16 +1403,12 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) /* sccnd.[bwl] dsp:[rd] */ static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) { - int dsp; - prt("sc%s.%c\t", cond[a->cd], size[a->sz]); if (a->ld < 3) { - dsp = rx_index_addr(a->sz, a->ld, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]", a->rd); + char dsp[8]; + rx_index_addr(ctx, dsp, a->sz, a->ld); + prt("sc%s.%c\t%s[r%d]", cond[a->cd], size[a->sz], dsp, a->rd); } else { - prt("r%d", a->rd); + prt("sc%s.%c\tr%d", cond[a->cd], size[a->sz], a->rd); } return true; }