| Message ID | 20200303004848.136788-1-palmerdabbelt@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3 | expand |
On Tue, 3 Mar 2020 at 00:48, Palmer Dabbelt <palmerdabbelt@google.com> wrote: > > The following changes since commit 8b6b68e05b43f976714ca1d2afe01a64e1d82cba: > > Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-02-27 19:15:15 +0000) > > are available in the Git repository at: > > git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf3 > > for you to fetch changes up to 5f3616ccceb5d5c49f99838c78498e581fb42fc5: > > hw/riscv: Provide rdtime callback for TCG in CLINT emulation (2020-02-27 13:46:37 -0800) > > ---------------------------------------------------------------- > RISC-V Patches for the 5.0 Soft Freeze, Part 3 > > This pull request is almost entirely an implementation of the draft hypervisor > extension. This extension is still in draft and is expected to have > incompatible changes before being frozen, but we've had good luck managing > other RISC-V draft extensions in QEMU so far. > > Additionally, there's a fix to PCI addressing and some improvements to the > M-mode timer. > > This boots linux and passes make check for me. Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0 for any user-visible changes. -- PMM
The following changes since commit 8b6b68e05b43f976714ca1d2afe01a64e1d82cba: Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-02-27 19:15:15 +0000) are available in the Git repository at: git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf3 for you to fetch changes up to 5f3616ccceb5d5c49f99838c78498e581fb42fc5: hw/riscv: Provide rdtime callback for TCG in CLINT emulation (2020-02-27 13:46:37 -0800) ---------------------------------------------------------------- RISC-V Patches for the 5.0 Soft Freeze, Part 3 This pull request is almost entirely an implementation of the draft hypervisor extension. This extension is still in draft and is expected to have incompatible changes before being frozen, but we've had good luck managing other RISC-V draft extensions in QEMU so far. Additionally, there's a fix to PCI addressing and some improvements to the M-mode timer. This boots linux and passes make check for me. ---------------------------------------------------------------- Alistair Francis (35): target/riscv: Convert MIP CSR to target_ulong target/riscv: Add the Hypervisor extension target/riscv: Add the Hypervisor CSRs to CPUState target/riscv: Add support for the new execption numbers target/riscv: Rename the H irqs to VS irqs target/riscv: Add the virtulisation mode target/riscv: Add the force HS exception mode target/riscv: Fix CSR perm checking for HS mode target/riscv: Print priv and virt in disas log target/riscv: Dump Hypervisor registers if enabled target/riscv: Add Hypervisor CSR access functions target/riscv: Add Hypervisor virtual CSRs accesses target/riscv: Add Hypervisor machine CSRs accesses target/riscv: Add virtual register swapping function target/riscv: Set VS bits in mideleg for Hyp extension target/riscv: Extend the MIE CSR to support virtulisation target/riscv: Extend the SIP CSR to support virtulisation target/riscv: Add support for virtual interrupt setting target/ricsv: Flush the TLB on virtulisation mode changes target/riscv: Generate illegal instruction on WFI when V=1 target/riscv: Add hypvervisor trap support target/riscv: Add Hypervisor trap return support target/riscv: Add hfence instructions target/riscv: Remove the hret instruction target/riscv: Only set TB flags with FP status if enabled target/riscv: Disable guest FP support based on virtual status target/riscv: Mark both sstatus and msstatus_hs as dirty target/riscv: Respect MPRV and SPRV for floating point ops target/riscv: Allow specifying MMU stage target/riscv: Implement second stage MMU target/riscv: Raise the new execptions when 2nd stage translation fails target/riscv: Set htval and mtval2 on execptions target/riscv: Add support for the 32-bit MSTATUSH CSR target/riscv: Add the MSTATUS_MPV_ISSET helper macro target/riscv: Allow enabling the Hypervisor extension Anup Patel (2): target/riscv: Emulate TIME CSRs for privileged mode hw/riscv: Provide rdtime callback for TCG in CLINT emulation Bin Meng (1): riscv: virt: Allow PCI address 0 hw/riscv/sifive_clint.c | 6 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 9 +- hw/riscv/virt.c | 3 +- include/hw/riscv/sifive_clint.h | 3 +- target/riscv/cpu.c | 57 ++- target/riscv/cpu.h | 63 +++- target/riscv/cpu_bits.h | 111 ++++-- target/riscv/cpu_helper.c | 486 ++++++++++++++++++++++--- target/riscv/csr.c | 455 ++++++++++++++++++++++- target/riscv/gdbstub.c | 11 +- target/riscv/insn32.decode | 22 +- target/riscv/insn_trans/trans_privileged.inc.c | 45 ++- target/riscv/op_helper.c | 71 +++- target/riscv/translate.c | 35 ++ 16 files changed, 1240 insertions(+), 141 deletions(-)